ui_test.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>
<meta http-equiv="content-type"
content="text/html; charset=ISO-8859-1">
<title>UI Test Review</title>
</head>
<body>
<div align="center">
<h1>BCP UI TEST REVIEW</h1>
<div align="center">
<div align="left">BCP UI tests consist of two parts: <br>
<ul>
<li>Tests ported from ARC tests</li>
</ul>
<ul>
<li>Tests added for BCP</li>
</ul>
<h2>1. Tests ported from ARC</h2>
(1) <a href="arc_usb_test.html">What ARC's test ?</a> <br>
(2) What tests are deleted?<br>
All otg tests are removed expept usb
id change test. <br>
<h2>2. New tests</h2>
(1) Usb clk tests<br>
Set USB tests to be sysclk/2, and run all ARC's
tests. It worked from 96MHz--100MHz, It is tested every Tue in nightly regression.
<br>
<br>
(2) USB attach/detach tests (Our OTG replacement)<br>
<br>
Put USB in disconnected host(master) mode:<br>
A) Connect Mini-A cable <br>
Check if we can get id-change
interrupt<br>
Check if usb_id is low.
<br>
Check to see if in control
reg, se0 is set to 1.<br>
B) Disconnect Mini-A cable<br>
Check if we can get id-change
interrupt<br>
Check if usb_id is asserted<br>
C) Attach low -speed device(Note: mini-A is connected
to BB in this case)<br>
Checked if we get attach interrupt<br>
Checked if usb-id is also changed
to 0.<br>
Check to see if in contron
reg, Jstate is set to 0 and se0 is set to 0. <br>
(please be aware of the difference
from case A)<br>
Enable pull-down resistors.<br>
D) Detached low-speed device<br>
Checked if we get the reset
interrupt.<br>
Disable pull-down resistors.<br>
E) Connect low-speed device again<br>
Check if we get attach interrupt
<br>
F) Disconnect Mini-A cable (device is also unplugged)<br>
Check if we get reset interrupt<br>
Check if usb_id is changed again(to
high)<br>
G) Do C)-F) with full speed device, everything should
be the same except in C)<br>
in ctrl reg, Jstate is asserted.
<br>
(can be used to determine what kind
of device is pluged in )<br>
Note, if we plugin mini-B cable/or host when BB is host,
we did not get any interrupts.<br>
<br>
Set BB in disconnected device(slave) mode:<br>
(A) Connected mini-A cable<br>
Check if we can get id-change interrupt<br>
Check if usb_id is low.<br>
Check to see if in control
reg, se0 is set to 1.<br>
(C) Set BB in disconnect device mode again, then connect
device(with mini-A cable)<br>
Check if we can get id-change
interrupt.<br>
Check if usb_id is low.<br>
Check to see if in control
reg, se0 is set to 0.<br>
(no attach interrupt in slave
mode)<br>
(D) Set BB in disconnect device mode again, then
connect mini-B cable<br>
Wait 3ms, and check if
we get some interrupt. (1ms does not count here)<br>
Note: We cannot
detect if mini-B cable is pluged in unless we connect host with it.<br>
(E) Connect a host<br>
Check if we get vbus
valid interrupt. <br>
Check if usb-id is asserted.<br>
(F) Disconnect the host<br>
Check if we get linestate
change interrupt. <br>
Check if usb-id
remaines high. <br>
(F) Repeat (E)<br>
(H) Disconnect mini-B cable (with host)<br>
Check if we get linestate change
interrupt. <br>
Check if usb-id remaines
high. <br>
(I) Connect a host with mini-B cable. <br>
Check if we get vbus valid interrupt.
<br>
Check if usb-id is asserted.<br>
<br>
(3) Usb sram tests<br>
Random read pre-filled data and compare. <br>
Random write date to sram and compare read back
data.<br>
( Do above 16 times in nightly)<br>
<br>
(4) USB security test<br>
In insecurity mode, verify we cannot r/w
sram and register<br>
Try to turn on usb security mode in insecurity
kernel mode, verify that we cannot r/w sram and reg either.<br>
Enter security mode and turn on USB bits, check
that we can rw sram and reg.<br>
Leave security mode, check that we still can r/w
sram and reg<br>
Turn off usb security bits, check that we cannot
r/w sram and reg again. <br>
<br>
(5) USB DMA error case check<br>
A) BDT entry is invalid (tested on both
reg and non-existing address)<br>
Verify if usb trasaction
failed and after it BB is still alive(can rw memory)<br>
B) Set usb buffer address to be invalid(
both reg and non-existing address)<br>
Verified if usb
trasaction failed and after it BB is still alive(can rw memory)<br>
<br>
(6) USB data transfer test<br>
A) Both controller run as device mode, and
run<br>
a) Do 1 bytes packet
OUT transaction through endpnt 0-15 twice, <br>
with random addr, random device id and ack back.<br>
(Let usb core access bdt sram as much as possible) <br>
b) Same as a), but
set bdt in memory instead of sram.<br>
c) Same as b), but
IN transaction<br>
d) Same as a), but
IN transaction<br>
e) Same as d), but
random IN/OUT transaction<br>
f) One do
IN transaction, the other do OUT transaction, <br>
with random device id, random ack back and random endpt with the following
size packets.<br>
0,
2, 3 , 4, 5, 6, 7, 8,9, 13, 16, 32,33, 64, 63, 128, 256, 512, 1023.<br>
Also let these packet crossing 1K, 2K, 4K, 16K, 32K, 64K, 128K, 256K, 512K,
1M, 2M and 4M memory boundaries.<br>
g) Random do IN/OUT/SETUP
transaction, with<br>
random packet length, random ack back, random device id, random buffer address
and random endpnt. <br>
B) Same as A), but one controller act as host,
the other as device.<br>
C) Same as A), but both in host mode.<br>
D) Run a) in A on one controller in host mode,
and make the other one idle.<br>
E) Run a) in A on one controller in device mode,
and make the other one idle.<br>
Note: * In host mode, all transaction send out/rcv
via endpnt 0.<br>
*
In host mode, we have to wait for sof interrupt about every 1ms.<br>
<br>
(7) USB low-speed data transfer test<br>
Do C) of 6) and D) of 6) with low speed device.
<br>
<h2>3. Coverage data and analysis</h2>
Let's take a look of 2003/01/05 nightly regression,
<br>
<br>
module: ui, ui_ioblk, ui_ctrl, ui_buf<br>
</div>
</div>
</div>
(1) Line: all of them are 100%<br>
(2) Condition: <br>
ui 16/18, others 100%<br>
These two line is not covered: <br>
nxt_CS0 = ((AC0 & Write_CS0)) ? CDataIn[0]
: CS0<br>
nxt_CS1 = ((AC1 & Write_CS1)) ? CDataIn[0]
: CS1 <br>
They are used to set sysclk/2 as usb clk, it should
be covered if we run (1) of 2. I will monitor it every Tue(sysclk=96MHz).<br>
(3) Toggle:<br>
<br>
<b>UI module:</b><br>
nxt_CAddrIn[0]
No No <br>
nxt_CAddrIn[25:24]
No No <br>
nxt_CAddrIn[26]
Yes No <br>
nxt_CAddrIn[27]
No No <br>
nxt_CAddrIn[28]
No Yes <br>
nxt_CAddrIn[31:29]
No No <br>
CAddrIn[0]
No No <br>
CAddrIn[25:24]
No No <br>
CAddrIn[26]
Yes No <br>
CAddrIn[27]
No No <br>
CAddrIn[28]
No Yes <br>
CAddrIn[31:29]
No No<br>
Those addr bit is not used in UI sram/Reg
space.<br>
<br>
usb_sel_sys
No No <br>
nxt_Write_CS0
No No <br>
nxt_CS0
No No <br>
nxt_Write_CS1
No No <br>
nxt_CS1
No No <br>
Write_CS0
No No <br>
CS0
No No <br>
Write_CS1
No No <br>
CS1
No No <br>
Those use for sysclk/2, action
is same as (2)<br>
<br>
usb_speed[1:0]
No No <br>
usbxr_fl[1:0]
No No <br>
For low speed device, to be done when
Bill add lowspeed support in bias.<br>
<br>
<b>usb_ioblk Module</b><br>
usb_suspnd
No No<br>
We does not support<br>
<br>
usb_speed
No No <br>
usbxr_fl
No No <br>
Low speed stuff. <br>
<br>
<b>ui_buf Module </b>
100%<br>
<br>
<b>ui_ctrl Module</b><br>
cbus_bdt_write_wait
No No <br>
nxt_cbus_bdt_write_wait
No No <br>
It is very hard to make those conflict.
We manually got those cases some times.<br>
<br>
t_address[0]
No No <br>
t_address[25:24]
No No <br>
t_address[26]
Yes No <br>
t_address[27]
No No <br>
t_address[28]
No Yes <br>
t_address[31:29]
No No <br>
Out of USB sram/reg space and it should
be 4 bytes aligned.<br>
<br>
usb_a_vbus_vld
No No <br>
usb_a_vbus_vld_n
No No <br>
usb_b_sess_end
No No <br>
usb_b_sess_end_n
No No <br>
usb_clk
No No <br>
usb_dm_high
No No <br>
usb_dm_low_n
No No <br>
usb_dp_low_n
No No <br>
usb_rst48_a
No No <br>
usb_rst_a
No No <br>
usb_sess_vld
No No <br>
usb_sess_vld_n
No No <br>
usb_vbus_chg
No No <br>
usb_vbus_chg_n
No No <br>
usb_vbus_dschg
No No <br>
usb_vbus_dschg_n
No No <br>
usb_vbus_vld_n
No No <br>
i_cmdack
No No <br>
i_reop
No No <br>
t_eop
No No <br>
t_rspack
No No <br>
t_be[3:0]
No No<br>
i_rspack
No No <br>
usb_suspnd
No No <br>
Those signal are not used.<br>
<br>
i_address[1:0]<br>
i_address[30:27] <br>
i_addr_reg[1:0]
No No <br>
i_addr_reg[30:27]
No No <br>
nxt_i_addr_reg[1:0]<br>
nxt_i_addr_reg[30:27]<br>
dma_addr[30:27]
No No<br>
Memory space is not available or memory
should be 4 bytes aligned<br>
<br>
t_wdata[31:8]
No No <br>
t_rdata[31:8]
No No <br>
UI register is less than 256. <br>
<br>
usb_speed
No No <br>
Low speed stuff.. <br>
<br>
length[6:3]
No No <br>
length[31:8]
No No <br>
hard wire to zero in verilog.<br>
<br>
(4) FSM: N/A<br>
<br>
<br>
</body>
</html>