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<html>
<head>
<title>
	Project BB - AC Specification
</title>
</head>
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  link="#004868" vlink="#986424" alink="#00ffff">

<table width="100%" cellpadding=2 cellspacing=0 border=0>
<tr>
<td bgcolor="#e0e0e0">
	Project BB - AC Specification
</td>
<td align=right bgcolor="#f0c0c0" width="20%">
<font color=red>
	<b>Broad<i>On</i> confidential</b>
</font>
</td>
</tr>
</table>

<p>
<b><u> Clocking </u></b>
<p>
	The BB chip contains the following clock domains.
<dl>
<dt> SYSCLK
<dd> The main clock of most of the logic. The input PAD_SYSCLK drives
	the SYSCLK tree and the memclk pll <i>pllx2</i>. It can also
	drive the usb clock domain if the supplied frequency is 96MHz.
<p>
<dt> MEMCLK (internal)
<dd> This is the clock for the DDR memory system. A pll (pllx2) multiplies
	SYSCLK by 2 and aligns the rising edge of MEMCLK to the rising edge
	of SYSCLK. The pll jitter and phase offsets must be taken into
	consideration for all clock paths between MEMCLK flops, and all
	paths between SYSCLK and MEMCLK.
<p>
<dt> VCLOCK
<dd> This is the clock for the video output logic. The pins PAD_VCLKI (input)
	and PAD_VCLKO (output) can be interfaced to a crystal directly, or
	to an external clock oscillator. The frequency depends on the video
	standard, PAL, NTSC or PAL-M, and if the video pll is used or not.
<p>
<dt> USBCLK
<dd> This is the clock for the USB interface logic. The pins PAD_USBCLKI
	(input) and PAD_USBCLKO (output) can be interfaced to a crystal
	directly, or to an external clock oscillator. A frequency of 48
	MHz is required by the USB core.
<p>
<dt> JTAGCLK, DBGCLK
<dd> These are essentially the same. The distinction was created to
	allow different timing constraints for mi internal logic versus the
	rest of the scan chains.
</dl>

<b> SYSCLK Operating Conditions </b>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Rating </td>
<td> Symbol </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
</tr>
<tr>
<td> Operating Frequency </td>
<td> f </td>
<td> 62.5 </td>
<td> 100 </td>
<td> MHz </td>
</tr>
<tr>
<td> Cycle Time </td>
<td> tC </td>
<td> 10 </td>
<td> 16 </td>
<td> ns </td>
</tr>
<tr>
<td> Duty Cycle </td>
<td> tH/tL </td>
<td> 48/52 </td>
<td> </td>
<td> % </td>
</tr>
<tr>
<td> Input Jitter </td>
<td> t[J] </td>
<td> </td>
<td> 250 </td>
<td> ps </td>
</tr>
</table>

<p>
<b> MEMCLK Operating Conditions </b>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Rating </td>
<td> Symbol </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
</tr>
<tr>
<td> Operating Frequency </td>
<td> f </td>
<td> 125 </td>
<td> 200 </td>
<td> MHz </td>
</tr>
<tr>
<td> Cycle Time </td>
<td> tC </td>
<td> 5 </td>
<td> 8 </td>
<td> ns </td>
</tr>
<tr>
<td> Duty Cycle <br> at end of MEMCLK tree </td>
<td> tH/tL </td>
<td> 48/52 </td>
<td> </td>
<td> % </td>
</tr>
<tr>
<td> PLL Output Phase Offset </td>
<td> t[J] </td>
<td> </td>
<td> -60/+120 </td>
<td> ps </td>
</tr>
<tr>
<td> PLL Output Jitter </td>
<td> t[J] </td>
<td> </td>
<td> +/-100 </td>
<td> ps </td>
</tr>
</table>

<p>
<b> VCLOCK Operating Conditions </b>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Rating </td>
<td> Symbol </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
</tr>
<tr>
<td> Operating Frequency, bypass mode </td>
<td> f(byp) </td>
<td> 40 </td>
<td> 50 </td>
<td> MHz </td>
</tr>
<tr>
<td> Cycle Time, bypass mode </td>
<td> tC(byp) </td>
<td> 20 </td>
<td> 25 </td>
<td> ns </td>
</tr>
<tr>
<td> Operating Frequency, pll mode </td>
<td> f(pll) </td>
<td> 14 </td>
<td> 18 </td>
<td> MHz </td>
</tr>
<tr>
<td> Cycle Time, pll mode </td>
<td> tC(pll) </td>
<td> 55 </td>
<td> 72 </td>
<td> ns </td>
</tr>
<tr>
<td> Duty Cycle <br> at end of VCLOCK tree </td>
<td> tH/tL </td>
<td> 45/55 </td>
<td> </td>
<td> % </td>
</tr>
<tr>
<td> PLL Output Phase Offset </td>
<td> t[J] </td>
<td> </td>
<td> -60/+120 </td>
<td> ps </td>
</tr>
<tr>
<td> PLL Output Jitter </td>
<td> t[J] </td>
<td> </td>
<td> +/-100 </td>
<td> ps </td>
</tr>
</table>

<p>
<b> USBCLK Operating Conditions </b>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Rating </td>
<td> Symbol </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
</tr>
<tr>
<td> Operating Frequency </td>
<td> f </td>
<td> 48 </td>
<td> 48 </td>
<td> MHz </td>
</tr>
<tr>
<td> Cycle Time </td>
<td> tC </td>
<td> 20.8 </td>
<td> 20.8 </td>
<td> ns </td>
</tr>
<tr>
<td> Frequency Tolerance </td>
<td> f[tol] </td>
<td> </td>
<td> 100 </td>
<td> ppm </td>
</tr>
<tr>
<td> Duty Cycle </td>
<td> tH/tL </td>
<td> 45/55 </td>
<td> </td>
<td> % </td>
</tr>
</table>

<p>
<b><u> IO Operating Conditions </u></b>
<p>

<p>
<b> Power/Reset Button Input </b>
<p>
	This is an asynchronous input sampled by SYSCLK. <br>
	The specified timing is relative to the end of the SYSCLK tree.
<pre>
  in      PAD_BUTTON
</pre>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 8 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> JoyChannel Ports </b>
<p>
	These are asynchronous ports driven and sampled by SYSCLK.<br>
	The specified timing is relative to the end of the SYSCLK tree.<br>
	The internal logic for sampling and deglitching is programmable.<br>
	Refer to the N64 JoyChannel Specification for protocol details.
<pre>
  io      PAD_JCHAN1, PAD_JCHAN2, PAD_JCHAN3
</pre>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Output Delay Time </td>
<td> t[co] </td>
<td> 1 </td>
<td> 5 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 8 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> Joystick Sensor Ports </b>
<p>
	These are asynchronous inputs sampled by SYSCLK.<br>
	The specified timing is relative to the end of the SYSCLK tree.<br>
	The internal logic for sampling and deglitching is programmable.<br>
	Refer to the joystick optical sensor specification for details.
<pre>
  in      PAD_LX0, PAD_LX1
  in      PAD_LY0, PAD_LY1
</pre>
<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 8 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> IDE IO Port </b>
<p>
	Below IO signals are driven from or sampled by SYSCLK. However,
	the bus itself is asynchronous. There is no io clock pin to which
	the timing can be referenced. PAD_SYSCLK can be used if the delay
	through the SYSCLK tree is taken into account.
<pre>
  out     PAD_IO_RST,
  bi      PAD_IO_AD0, PAD_IO_AD1, PAD_IO_AD2, PAD_IO_AD3,
  bi      PAD_IO_AD4, PAD_IO_AD5, PAD_IO_AD6, PAD_IO_AD7,
  bi      PAD_IO_AD8, PAD_IO_AD9, PAD_IO_AD10, PAD_IO_AD11,
  bi      PAD_IO_AD12, PAD_IO_AD13, PAD_IO_AD14, PAD_IO_AD15,
  out     PAD_IO_ALE,
  out     PAD_IO_CS0, PAD_IO_CS1, PAD_IO_CS2, PAD_IO_CS3,
  out     PAD_IO_IOR, PAD_IO_IOW,
  in      PAD_IO_DMARQ,
  out     PAD_IO_DMACK,
  in      PAD_IO_INTR,
</pre>

<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Output Delay Time </td>
<td> t[co] </td>
<td> 1 </td>
<td> 5 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 5 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> Flash Port </b>
<p>
	Below IO signals are driven from or sampled by SYSCLK. However,
	the bus itself is asynchronous. There is no io clock pin to which
	the timing can be referenced. PAD_SYSCLK can be used if the delay
	through the SYSCLK tree is taken into account. Details about the
	NAND flash io protocol can be found in the respective device data
	sheets. The flash timing is programmable.
<pre>
  out     PAD_FL_CE0, PAD_FL_CE1, PAD_FL_CE2, PAD_FL_CE3,
  out     PAD_FL_ALE, PAD_FL_CLE,
  out     PAD_FL_RE, PAD_FL_WE, PAD_FL_WP,
  in      PAD_FL_RYBY, PAD_FL_MD,
</pre>

<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Output Delay Time </td>
<td> t[co] </td>
<td> 1 </td>
<td> 5 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 8 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> Generic IO Port </b>
<p>
	Below IO signals are driven from or sampled by SYSCLK. However,
	the bus itself is asynchronous. There is no io clock pin to which
	the timing can be referenced. PAD_SYSCLK can be used if the delay
	through the SYSCLK tree is taken into account. The port direction
	is programmable.
<pre>
  bi      PAD_GPIO0, PAD_GPIO1, PAD_GPIO2, PAD_GPIO3,
</pre>

<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> Rise Time </td>
<td> t[r] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Fall Time </td>
<td> t[f] </td>
<td> </td>
<td> 3 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Output Delay Time </td>
<td> t[co] </td>
<td> 1 </td>
<td> 5 </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Setup Time </td>
<td> t[su] </td>
<td> 8 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
<tr>
<td> Input Hold Time </td>
<td> t[h] </td>
<td> 1 </td>
<td>  </td>
<td> ns </td>
<td> load 25pF </td>
</tr>
</table>

<p>
<b> DDR Memory Interface </b>
<p>
	The PAD_MCLK0 and PAD_MCLK1 pins provide the multiplied DDR clock
	to the external memory chips. There are board delays for the DDR
	clock which center the sampling of the DDR address (PAD_MADDR*,
	PAD_MBANK*) and controls (PAD_MRAS, PAD_MCAS, PAD_MWE and PAD_MCKE)
	by the DDR chip.

<pre>
  out     PAD_MCLK0, PAD_MCLK1
  out     PAD_MADDR*, PAD_MBANK*
  out     PAD_MRAS, PAD_MCAS, PAD_MWE, PAD_MCKE
  bi      PAD_MDATA*
  bi      PAD_MDQS
</pre>

	The DDR strobes (PAD_MDQS*) also have board delays of approximately
	1/4 MEMCLK period to center the sampling of the data (PAD_MDATA*).
	There is one strobe per 8 data bits. Each of these byte lanes function
	as a source synchronous interface. The grouping of data to strobe
	signals is listed below.

<pre>
  PAD_MDQS3    PAD_MDATA[31:24]
  PAD_MDQS2    PAD_MDATA[23:16]
  PAD_MDQS1    PAD_MDATA[15:8]
  PAD_MDQS0    PAD_MDATA[7:0]
</pre>

<table cellpadding=2 cellspacing=0 border=1>
<tr>
<td> Symbol </td>
<td> Rating </td>
<td> Min </td>
<td> Max </td>
<td> Unit </td>
<td> Condition </td>
</tr>
<tr>
<td> PAD_MCLK* skew  </td>
<td> t[mclk-skew] </td>
<td> </td>
<td> 100 </td>
<td> ps </td>
<td> load 15pF <br>
	MCLK0 rise to MCLK1 fall <br>
	MCLK0 fall to MCLK1 rise </td>
</tr>
<tr>
<td> PAD_MCLK* Output Delay Time <br>
	MEMCLK to MCLK* pins </td>
<td> t[mclk-delay] </td>
<td> 1.2 </td>
<td> 1.4 </td>
<td> ns </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Address/Control Output Delay Time <br>
	relative to MCLK0 falling and MCLK1 rising </td>
<td> t[askew] </td>
<td> -100 </td>
<td> 600 </td>
<td> ps </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Data Output Delay <br>
	MDQS* to MDATA* within group <br>
	both rising and falling edges </td>
<td> t[dqsq] </td>
<td> -350 </td>
<td> 350 </td>
<td> ps </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Output Skew between MDQS* <br>
	both rising and falling edges </td>
<td> t[dqs-skew] </td>
<td> -100 </td>
<td> 100 </td>
<td> ps </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Output Enable Time <br>
<td> t[on] </td>
<td> 0 </td>
<td> 2 </td>
<td> ns </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Output Disable Time <br>
<td> t[z] </td>
<td> 0 </td>
<td> 2 </td>
<td> ns </td>
<td> load 15pF </td>
</tr>
<tr>
<td> Input Setup/Hold Time <br>
	MDATA* to MDQS* within group <br>
	both rising and falling edges of MDQS* </td>
<td> t[dq-su] </td>
<td> -250 </td>
<td> 250 </td>
<td> ps </td>
<td> load 15pF, (1) </td>
</tr>
</table>

(1) after insertion of 250ps delays into MDATA* paths;

<hr>
<font size="-1">
	Problems and comments to
<a href="mailto:berndt@broadon.com">
	berndt@broadon.com
</a>
</font>
</body>
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