addr-space.html
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<html>
<head>
<title>
Project BB - Physical Address Spaces
</title>
</head>
<body bgcolor="#ffffff" text="#000000"
link="#004868" vlink="#986424" alink="#00ffff">
<table width="100%" cellpadding=2 cellspacing=0 border=0>
<tr>
<td bgcolor="#e0e0e0">
Project BB - Physical Address Spaces
</td>
<td align=right bgcolor="#f0c0c0" width="20%">
<font color=red>
<b>Broad<i>On</i> confidential</b>
</font>
</td>
</tr>
</table>
<p>
<b> Physical Address Spaces </b>
<p>
The physical address spaces from the CPU's point of view are listed below.
Remember that physical addresses greater equal 0x20000000 must be mapped
through the TLB in 32-bit mode. The kseg0 and kseg1 address spaces both
map to the physical addresses range 0x0 through 0x1fffffff (512MBytes max).
<p>
<pre>
The PI registers show up in the RCP register space.
The PI maps the cartridge domain 1 and 2 spaces into the AD16 bus.
Domain 1 and 2 allowed for different device timings.
address range size N64
------------------------------------------------------------
0x80000000 ... 0xffffffff 2GB external SYSAD
0x1fd00000 ... 0x7fffffff 1.5GB cartridge domain 1
0x1fc00800 ... 0x1fcfffff 1MB-2k reserved
0x1fc007fc ... 0x1fc007ff 4B PIF status
0x1fc007c0 ... 0x1fc007ff 64B PIF RAM
0x1fc00000 ... 0x1fc007bf 1984B PIF boot ROM
0x10000000 ... 0x1fbfffff 252MB cartridge domain 1
0x08000000 ... 0x0fffffff 128MB cartridge domain 2
0x06000000 ... 0x07ffffff 32MB cartridge domain 1
0x05000000 ... 0x05ffffff 16MB cartridge domain 2
0x04000000 ... 0x04ffffff 16MB RCP registers
0x03f00000 ... 0x03ffffff 1MB RDRAM registers
0x00800000 ... 0x03efffff 55MB reserved
0x00000000 ... 0x007fffff 8MB RDRAM memory
</pre>
<p>
In BB, the PI device interface becomes an internal interface to the
io bus controllers, external NAND flash interface and smart-media slot.
The internal flash (iflash) and sram (isram) are part of the MI module.
Accesses to these two address spaces are not seen on the cbus.
<p>
The BB address map is compatible with the rcp address map. The RDRAM
register space is now reserved. Game code accessing these registers for
whatever reason will not be able to modify them or anything else in that
space. The internal flash and sram appear in a previously reserved
address space. For more details on the io system see the
<a href="pi-spec.html">PI Specification</a>.
<pre>
All existing and new registers show up in the RCP register space.
The PI maps the io space into selects for the io devices.
The 64 bytes of controller RAM space are not accessible as iflash.
address range size dev BB
--------------------------------------------------------------------------------
0x80000000 ... 0xffffffff 2GB ri all main memory x64 mode
0x1fd00000 ... 0x7fffffff 1.5GB pi io space 1
0x1fcc0000 ... 0x1fcfffff 256kB - reserved
0x1fc80000 ... 0x1fcbffff 256kB - internal enet memory
0x1fc40000 ... 0x1f7fffff 256kB mi isram
0x1fc00800 ... 0x1f37ffff 254kB mi iflash
0x1fc007c0 ... 0x1fc007ff 64B si controller RAM
0x1fc00000 ... 0x1fc007bf 1984B mi iflash, first 1984 bytes
0x10000000 ... 0x1fbfffff 252MB pi io space 1
0x08000000 ... 0x0fffffff 128MB pi io space 2
0x06000000 ... 0x07ffffff 32MB pi io space 1
0x05000000 ... 0x05ffffff 16MB pi io space 2
0x04000000 ... 0x04ffffff 16MB all rcp registers
0x03000000 ... 0x03ffffff 16MB - reserved, reads X, writes dropped
0x01000000 ... 0x02ffffff 32MB ri lower main memory x64 mode
0x00000000 ... 0x00ffffff 16MB ri lower main memory x36 mode
</pre>
<hr>
<font size="-1">
Problems and comments to
<a href="mailto:berndt@broadon.com">
berndt@broadon.com
</a>
</font>
</body>
</html>