dbg-prog.html
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<html>
<head>
<title>
Project BB - Debug Board Programming Specification
</title>
</head>
<body bgcolor="#ffffff" text="#000000"
link="#004868" vlink="#986424" alink="#00ffff">
<table width="100%" cellpadding=2 cellspacing=0 border=0>
<tr>
<td bgcolor="#e0e0e0">
Project BB - Debug Board Programming Specification
</td>
<td align=right bgcolor="#f0c0c0" width="20%">
<font color=red>
<b>Broad<i>On</i> confidential</b>
</font>
</td>
</tr>
</table>
<a name="arch">
<p>
<b><u> Debug Board Architecture </u></b>
<p>
The Debug Board is a piece of hardware that bridges a PC with the
BB player, and that is used to interface the BB chip to JTAG. The
interface on the PC side requires a parallel port that is IEEE1284 SPP
and EPP compliant. The interface on the BB player side is the IDE bus
on the BB chip. All the required logic is implemented in a FPGA on the
debug board. The FPGA is SRAM based, ie. it needs configuration after
power-up or device reset. The JTAG interface bypasses the FPGA.
<a name="jtag">
<p>
<b><u> JTAG Interface </u></b>
<p>
The JTAG interface requires the parallel port to run in SPP mode.
In this mode, all parport data and control lines are directly driven
by registers. Software is responsible for driving the correct protocol
and timing. Below table defines the interface.
<p>
<dl>
<dd>
<table cellspacing=1 cellpadding=2 border=1>
<tr>
<td> JTAG signal </td>
<td> parport signal </td>
<td> direction </td>
<td> description </td>
</tr>
<tr>
<td> TDI </td>
<td> DATA[2] </td>
<td> PC -> BB </td>
<td> JTAG data in </td>
</tr>
<tr>
<td> TMS </td>
<td> DATA[1] </td>
<td> PC -> BB </td>
<td> JTAG mode </td>
</tr>
<tr>
<td> TCK </td>
<td> DATA[0] </td>
<td> PC -> BB </td>
<td> JTAG clock </td>
</tr>
<tr>
<td> TDO </td>
<td> BUSY (pin 11) </td>
<td> PC <- BB </td>
<td> JTAG data out </td>
</tr>
</table>
</center>
</dl>
<a name="jtag">
<p>
<b><u> Debug Interface </u></b>
<p>
The FPGA implements a 2kByte data buffer and two semaphores per direction.
The entire data buffer can be accessed from either side. It is left to the
software to partition the buffer for message exchanges. There are two
semaphores in each direction to allow independent streams in both directions.
The parallel port must be in EPP mode after the FPGA has been configured.
The parport side has independent read and write pointers, as there is no
direct addressing possible. The ide side uses direct addressing, ie. the
entire 2kByte buffer and the control register appear as address spaces.
<p>
<dl>
<dt> EPP Address write cycles write the control register.
<dt> Multiple bits can be set in the 00xx_xxxx class.
<p>
<dd>
<table cellspacing=1 cellpadding=2 border=1>
<th colspan=2> EPP Address Write Cycle </th>
<tr>
<td> Data[7:0] </td>
<td> Operation </td>
</tr>
<tr>
<td> 10ww_wwww </td>
<td> sets the write pointer to w*32 </td>
</tr>
<tr>
<td> 11ww_wwww </td>
<td> sets the read pointer to r*32 </td>
</tr>
<tr>
<td> 01xx_xxxx </td>
<td> resets the parport interface; <br>
clears the host->bb semaphores; <br>
clears the host<-bb interrupts; <br>
set write and read pointers to 0;
</td>
</tr>
<tr>
<td> 00xx_xxx1 </td>
<td> sets host->bb request and issues bb interrupt </td>
</tr>
<tr>
<td> 00xx_xx1x </td>
<td> sets host->bb ack and issues bb interrupt </td>
</tr>
<tr>
<td> 00xx_x1xx </td>
<td> clears host<-bb request and interrupt </td>
</tr>
<tr>
<td> 00xx_1xxx </td>
<td> clears host<-bb ack and interrupt </td>
</tr>
</table>
</dl>
<dl>
<dt> EPP Address read cycles return the status byte.
<p>
<dd>
<table cellspacing=1 cellpadding=2 border=1>
<th colspan=2> EPP Address Read Cycle </th>
<tr>
<td> Bit </td>
<td> Description </td>
</tr>
<tr>
<td> 0 </td>
<td> 1 = outgoing request; <br>
raises ide port IRQ; <br>
active until cleared by ide side;
</td>
</tr>
<tr>
<td> 1 </td>
<td> 1 = outgoing ack; <br>
raises ide port IRQ; <br>
active until cleared by ide side;
</td>
</tr>
<tr>
<td> 2 </td>
<td> 1 = incoming request; <br>
raises parallel port IRQ; <br>
active until cleared by writing 00xx_x1xx
</td>
</tr>
<tr>
<td> 3 </td>
<td> 1 = incoming ack; <br>
raises parallel port IRQ; <br>
active until cleared by writing 00xx_1xxx
</td>
</tr>
<tr>
<td> 7:4 </td>
<td> return 0 </td>
</tr>
</table>
</dl>
<p>
<dl>
<dt> IDE accesses to PI_IDE0 + 0x0000 read/write the data buffer.
<dt> IDE write cycles to PI_IDE0 + 0x8000 write the control register.
<dt> Multiple bits can be set in the 00xx_xxxx class.
<p>
<dd>
<table cellspacing=1 cellpadding=2 border=1>
<th colspan=2> IDE Write to PI_IDE0 + 0x8000 </th>
<tr>
<td> Data[15:0] </td>
<td> Operation </td>
</tr>
<tr>
<td> xxxx_xxxx_01xx_xxxx </td>
<td> resets the IDE interface; <br>
clears the host<-bb semaphores; <br>
clears the host->bb interrupts; <br>
</td>
</tr>
<tr>
<td> xxxx_xxxx_00xx_xxx1 </td>
<td> sets host<-bb request and issues bb interrupt </td>
</tr>
<tr>
<td> xxxx_xxxx_00xx_xx1x </td>
<td> sets host<-bb ack and issues bb interrupt </td>
</tr>
<tr>
<td> xxxx_xxxx_00xx_x1xx </td>
<td> clears host->bb request and interrupt </td>
</tr>
<tr>
<td> xxxx_xxxx_00xx_1xxx </td>
<td> clears host->bb ack and interrupt </td>
</tr>
</table>
</dl>
<dl>
<dt> IDE read cycles to PI_IDE0 + 0x8000 read the status register.
<p>
<dd>
<table cellspacing=1 cellpadding=2 border=1>
<th colspan=2> IDE Reads from PI_IDE0 + 0x8000 </th>
<tr>
<td> Bit </td>
<td> Description </td>
</tr>
<tr>
<td> 0 </td>
<td> 1 = outgoing request; <br>
raises host port IRQ; <br>
active until cleared by host side;
</td>
</tr>
<tr>
<td> 1 </td>
<td> 1 = outgoing ack; <br>
raises host port IRQ; <br>
active until cleared by host side;
</td>
</tr>
<tr>
<td> 2 </td>
<td> 1 = incoming request; <br>
raises bb ide IRQ; <br>
active until cleared by writing 00xx_x1xx
</td>
</tr>
<tr>
<td> 3 </td>
<td> 1 = incoming ack; <br>
raises bb ide IRQ; <br>
active until cleared by writing 00xx_1xxx
</td>
</tr>
<tr>
<td> 15:4 </td>
<td> return 0 </td>
</tr>
</table>
</dl>
<a name="config">
<p>
<b><u> FPGA Configuration </u></b>
<p>
The libdbp.a contains a function to configure the FPGA.
The configuration code is a byte array included from the file
rf/hw/debug/dbx/dbx.c . The tools to compile the FPGA verilog into
a configuration binary run on a PC under Windows2000.
<br>
XXX more here.
<a name="rework">
<p>
<b><u> Debug Board Rework </u></b>
<p>
<li> remove R201 and R207
<li> move R218 to R217
<li> add caps C310, C311, C312, C313
<hr>
Problems and comments to
<a href="mailto:berndt@broadon.com">
berndt@broadon.com
</a>
</font>
</body>
</html>