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<h1>Bring Up/Development System</h1>
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<h3>Assumptions:</h3>
- BB chip back March 21st, 1 month to evaluate it.<br>
- Development and evt production systems are not available at the same time.
&nbsp;Evt1 boards are available a week or two later. &nbsp;Bring up/eval
work is done with dev system.<br>
- Use early layout of evt1 as the dev(p0) board. &nbsp;Add a header with
jtag and ide signals for debug.<br>
- Production memory module isn't available at bring-up time (with 64MB).
&nbsp;Instead hack up some prototype versions from old cartridges. &nbsp;Issue
is whether plastic shroud is necessary to hold module in place.<br>
- Use modified n64 controller dongle attached to dev system. <br>
- Mechanical assemblies not available until mid-April, so most ch<br>
- Dummy controllers are available for testing serial interface<br>
- Breakout box of some sort available for testing controllers and USB<br>
- Need ~5 working dev systems to complete evaluation.<br>
<h3>System Bring Up/Chip Verification Requirements:</h3>
<h4>Hardware:</h4>
BB Chip Pin Accessibility<br>
Ability to change sysclock oscillator,&nbsp; video clock and usb clock crystals<br>
Ability to change BoxID strappings (clocks, memconfig)<br>
Power regulator bypass (in case power circuit has problems).<br>
Power Control with bypass (so software doesn't have to assert power good)
.<br>
PC &lt;-&gt;JTAG&nbsp; interface - to load virage, load boot ram, etc.<br>
PC&lt;-&gt;BB debug interface, using chip IDE<br>
PC&lt;-&gt;FLASH interface to write code to flash <br>
DDR x32, x16 configuration<br>
Video NTCS, PAL, MPAL configuration<br>
2xUSB connectors<br>
A/V connectors<br>
Power/Error LEDs<br>
<br>
The flash writing solution must be efficient(fast) since we will likely be
doing a large number of edit/compile/write iterations during bringup and
debug. &nbsp;We should also decide if loading directly to DRAM via JTAG is
a viable development option.<br>
<h4>Software:</h4>
PC JTAG control software<br>
PC FLASH read/write software (and bits to put in flash)<br>
PC debug interface software, including gdb remote debug module.<br>
<br>
Virage bits<br>
Bootram bits (just in case)<br>
Faux secure kernel, test program, 2nd level boot<br>
Test applications<br>
<h4>Tools:</h4>
Oscilloscope<br>
Logic analyzer<br>
CATC USB analyzer<br>
TVs (capable of PAL, MPAL, NTSC)<br>
<br>
Slave controllers<br>
USB devices (modem, ethernet, storage, PC)<br>
<br>
<br>
<h3>Bring Up Sequence:</h3>
Test board/chip power/IO integrity, clocks, etc.<br>
<br>
Test JTAG access, test chip components through jtag<br>
<ul>
  <li>chain integrity/bypass/id test<br>
  </li>
  <li>virage</li>
  <li>boot ram</li>
  <li>debug</li>
  <li>srams/dram<br>
  </li>
</ul>
CPU/FLASH sanity<br>
<ul>
  <li>boot rom, verify debug I/O writes</li>
  <li>verify sk flash dma/aes read/boot</li>
  <li>verify PC debug interface (printf)</li>
  <li>Power control<br>
  </li>
</ul>
Subsystems<br>
<ul>
  <li>DRAM</li>
  <li>MI (secure mode, power off, sec timer, virage programming)</li>
  <li>PI (ATB, AES, GPIO)</li>
  <li>SI<br>
  </li>
  <li>VI/AI<br>
  </li>
  <li>SP/DP</li>
  <li>USB</li>
  <ul>
    <li>modem</li>
    <li>storage</li>
    <li>PC</li>
    <li>ethernet/wireless</li>
  </ul>
  <li>Breakout box &nbsp;serial controllers, slave mode</li>
</ul>
Grandslam test<br>
<ul>
  <li>Bootrom + SK + FirstApp + Mario64</li>
  <li>Assume have mini -SK that can bootstrap a game too so that we aren't
dependent on fully functionally SK or FirstApp to run games.<br>
  </li>
</ul>
Questions:<br>
<br>
What tests to port from verif environment?<br>
What "apps" to run from the apps directory?<br>
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