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<title>
	Project BB - MI Specification
</title>
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<table width="100%" cellpadding=2 cellspacing=0 border=0>
<tr>
<td bgcolor="#e0e0e0">
	Project BB - MI Specification
</td>
<td align=right bgcolor="#f0c0c0" width="20%">
<font color=red>
	<b>Broad<i>On</i> confidential</b>
</font>
</td>
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</table>

<p>
<b><u> Index </u></b>
<p>
<dl>
<dd> <a href="vr4300-man.pdf">NEC Vr4300 User's Manual</a>
<dd> <a href=#arch>MI Architecture</a>
<dd> <a href=#reqtypes>CPU Request Types</a>
<dd> <a href=#berr>Bus Error Handling</a>
<dd> <a href=#addrspc>Memory and Register Spaces</a>
<dd> <a href=#comregs>Compatible MI Registers</a>
<dd> <a href=#newregs>New MI Registers</a>
<dd> <a href=#reset>Reset</a>
<dd> <a href=#intr>Interrupts</a>
<dd> <a href=#virage>Virage Interface and Control</a>
</dl>

<a name="arch">
<p>
<b><u> MI Architecture </u></b>
<p>
	NECs embedded Vr4300 core features an unidirectional SYSAD interface.
	The only difference to the chip version is that the bi-directional
	drivers have been removed. The protocol itself has not changed, there
	can still be only one outstanding request. BroadOn has requested from
	NEC support for PLL clock multipliers of x1, x1.5 and x2.
<p>
<img src="mi-unibus.gif" width=640 height=214 border=0>
<p>
	The MI is pretty much a pass-through block between the proceesor's
	SYSAD interface and the system's control bus (cbus) and the data bus
	(dbus). Five new blocks implement new functions and security features.
	The <i>security module</i> controls system wide access to security
	sensitive information, as well as entering and leaving of
<a href="secure-mode.html">secure mode</a>.
	The <i>Boot ROM</i> (brom) contains the boot loader that brings in
	the <i>secure kernel</i> from external flash into the <i>boot SRAM</i>
	(bram) for execution. The <i>iram</i> can be configured for secure
	or application mode, its general purpose is emulation support. Three
	<i>Virage Flash Blocks</i> (v0, v1, and v2) contain security related
	data. Flash v0 and v1 store 512bits (16 words x32). Flash v2 is 2kbits
	in size (64 words x32) and contains fixed security bits, such as the
	private key. It is programmed through the JTAG chain and can be used
	to patch code.
<p>
<img src="mi-block.gif" width=640 height=480 border=0>

<a name="reqtypes">
<p>
<b><u> CPU Request Types </u></b>
<p>
	The cpu can issue two basic types of requests; single and block requests.
	Single requests are triggered by accesses to uncached or write-through
	spaces and move 1..4 bytes of data. Block requests of size 8 (doubleword)
	are issued by doubleword loads or stores to uncached or write-through
	spaces and move exactly 8 bytes. They are only issued when the cpu is
	in 64-bit mode. Block requests of size 16 move a data cache line between
	the cpu and cacheable memory. Block requests of size 32 move an instruction
	cache line.

<a name="berr">
<p>
<b><u> Bus Error Handling </u></b>
<p>
	The SYSAD bus has no means to signal a failed write request back to the
	cpu pipe. The only way to aid debug and access control is through external
	interrupts or nmi. Logic in the MI has to capture the invalid address,
	access type and write data for the exception or emulation handler. A cycle
	accurate restart is impractical when interrupts are used, because the
	program counter in the cpu pipe can advance during disabled interrupts.
	Besides, large error state storage and instruction backtrace in software
	would be required. To fully emulate cycle accuracy, nmi must be used.
	Erroneous read requests can signal a bus error in the read response to
	the cpu. A cpu pipeline restart is possible. The BB MI has only one
	capture register to hold the first failed write. Multiple write errors
	before the registers have been read, set a <i>multiple bit</i>. A <i>write
	error interrupt</i> is raised upon capture of a failed write.

<a name="addrspc">
<p>
<b><u> Memory and Register Spaces </u></b>
<p>
	The system implementation of the control bus (cbus) and data bus (dbus)
	puts access limits on various address spaces. Main memory (dbus bus
	through ri), the boot ROM (brom), the boot SRAM (bram), the internal sram
	(iram), and all virage shadow SRAMs (v0, v1, v2) are the only spaces
	that support both single (uncached) and block (cached) accesses. All
	other spaces are defined as register spaces and only support single
	reads and writes because they use the cbus. Furthermore, all register
	space accesses read or write all 32 bits of data, thus forcing 32-bit
	alignment of addresses without byte write capability. The behavior for
	block requests to register spaces is programmable. Illegal block reads
	can either return a bus error to invalidate the cache line, or return
	undefined data. Illegal block writes can be ignored, raise the write error
	interrupt or raise the secure kernel trap.
	Below table lists the MI actions in the various address spaces.
	If a particular memory device is smaller than the listed space, then the
	device appears mirrored multiple times.
<pre>
	address range			size	dev	MI
	--------------------------------------------------------------------------------
	0x80000000 ... 0xffffffff	2GB	ri	cbus dma request
	0x1fd00000 ... 0x7fffffff	1.5GB	pi	io 1, cbus read/write request
	0x1fcc0000 ... 0x1fcfffff	256kB	mi	writes ignored, reads 0;
	0x1fcb0000 ... 0x1fcbffff	64kB	mi	writes ignored, reads 0;
	0x1fca0000 ... 0x1fcaffff	64kB	mi	virage 2, 2kbits;
	0x1fc90000 ... 0x1fc9ffff	64kB	mi	virage 1, 512bits;
	0x1fc80000 ... 0x1fc8ffff	64kB	mi	virage 0, 512bits;
	0x1fc80000 ... 0x1fcbffff	256kB	mi	virage flash space
	0x1fc40000 ... 0x1f7fffff	256kB	mi	iram, no cbus request
	0x1fc00800 ... 0x1f37ffff	254kB	mi	brom/bram, no cbus request
	0x1fc007c0 ... 0x1fc007ff	64B	mi	brom/bram, no cbus request
							optional bus/write error
	0x1fc00000 ... 0x1fc007bf	1984B	mi	brom/bram, no cbus request
	0x10000000 ... 0x1fbfffff	252MB	pi	io 1, cbus read/write request
	0x08000000 ... 0x0fffffff	128MB	pi	io 2, cbus read/write request
	0x06000000 ... 0x07ffffff	32MB	pi	io 1, cbus read/write request
	0x05000000 ... 0x05ffffff	16MB	pi	io 2, cbus read/write request
	0x04300000 ... 0x043fffff	1MB	mi	mi registers, no cbus request
	0x04000000 ... 0x04ffffff	16MB	all	cbus read/write request
	0x03000000 ... 0x03ffffff	16MB	mi	writes dropped, reads return 0
							optional bus/write error
	0x01000000 ... 0x02ffffff	32MB	ri	cbus dma request
	0x00000000 ... 0x00ffffff	16MB	ri	cbus dma request
</pre>

<a name="comregs">
<p>
<b><u> Compatible MI Registers </u></b>
<p>
	Below table lists all compatible MI registers. None of the special
	modes that were enabled through the MI_MODE register in N64 are
	implemented. The RDRAM register mode has been replaced by registers
	in the RI for configuration of the main memory interface. The ebus
	test mode is not needed, because the x64 main memory space allows
	access to all bits of the DDR memory. The init mode has been removed
	as well. It was also related to RDRAM setup. Scan and JTAG cover
	manufacturing and debug requirements.
<p>
<table cellpadding=2 cellspacing=2 border=1>
<tr>
<td> Name </td>
<td> Address </td>
<td> Data </td>
<td> Read/Write </td>
<td> Reset </td>
<td> N64 </td>
<td> Description </td>
</tr>

<tr>
<td> MI_MODE </td>
<td> 0x0430_0000 </td>
<td> [31:14] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> write data are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> set RDRAM register mode; <br>
	ignored in bcp; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [12] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> clear RDRAM register mode; <br>
	ignored in bcp; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11] </td>
<td> W CLR_DPINTR </td>
<td> - </td>
<td> y </td>
<td> clear DP interrupt; <br>
	writing 1 clears DP interrupt; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [10] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> set ebus test mode; <br>
	ignored in bcp; <br>
	ebus test is covered by scan/jtag; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [9] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> clear ebus test mode; <br>
	ignored in bcp; <br>
	ebus test is covered by scan/jtag; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [8] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> set init mode; <br>
	ignored in bcp; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> clear init mode; <br>
	ignored in bcp; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [6:0] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> init mode length; <br>
	ignored in bcp; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:10] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> reads return 0; </td>
<tr>
<td> </td>
<td> </td>
<td> [9] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> RDRAM register mode; <br>
	bcp returns 0 as there is no such mode; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [8] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> ebus test mode; <br>
	bcp returns 0 as there is no such mode; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> init mode; <br>
	bcp returns 0 as there is no such mode; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [6:0] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> init mode length; <br>
	bcp returns 0 as there is no such mode; <br>
</td>
</tr>

<tr>
<td> MI_VERSION </td>
<td> 0x0430_0004 </td>
<td> [31:0] </td>
<td> RO VERSION </td>
<td> 0x0202b0b0 </td>
<td> y </td>
<td> version number, same as N64; <br>
	[31:24] is RSP version; <br>
	[23:16] is RDP version; <br>
	[15:8] is RI version; <br>
	[7:0] is IO version; <br>
	writes are ignored; <br>
</td>
</tr>

<tr>
<td> MI_INTR </td>
<td> 0x0430_0008 </td>
<td> [31:0] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> writes are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:6] </td>
<td> RO </td>
<td> 0 </td>
<td> y </td>
<td> reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5] </td>
<td> RO DP_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of dp interrupt; <br>
	set by dp unit; <br>
	cleared by writing 1 to MI_MODE bit 11; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [4] </td>
<td> RO PI_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of pi dma interrupt; <br>
	set and cleared by pi dma; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3] </td>
<td> RO VI_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of vi interrupt; <br>
	set and cleared by vi; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [2] </td>
<td> RO AI_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of ai interrupt; <br>
	set and cleared by ai; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1] </td>
<td> RO SI_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of si interrupt; <br>
	set and cleared by si; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> RO SP_INTR </td>
<td> 0 </td>
<td> y </td>
<td> status of sp interrupt; <br>
	set and cleared by sp; <br>
</td>
</tr>

<tr>
<td> MI_MASK </td>
<td> 0x0430_000c </td>
<td> [31:12] </td>
<td> W </td>
<td> - </td>
<td> y </td>
<td> writes are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11:10] </td>
<td> W <br> SET_DP_MASK <br> CLR_DP_MASK </td>
<td> - </td>
<td> y </td>
<td> writing 10 sets dp interrupt mask; <br>
	writing 01 clears dp interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [9:8] </td>
<td> W <br> SET_PI_MASK <br> CLR_PI_MASK</td>
<td> - </td>
<td> y </td>
<td> writing 10 sets pi interrupt mask; <br>
	writing 01 clears pi interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7:6] </td>
<td> W <br> SET_VI_MASK <br> CLR_VI_MASK</td>
<td> - </td>
<td> y </td>
<td> writing 10 sets vi interrupt mask; <br>
	writing 01 clears vi interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5:4] </td>
<td> W <br> SET_AI_MASK <br> CLR_AI_MASK </td>
<td> - </td>
<td> y </td>
<td> writing 10 sets ai interrupt mask; <br>
	writing 01 clears ai interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3:2] </td>
<td> W <br> SET_SI_MASK <br> CLR_SI_MASK </td>
<td> - </td>
<td> y </td>
<td> writing 10 sets si interrupt mask; <br>
	writing 01 clears si interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1:0] </td>
<td> W <br> SET_SP_MASK <br> CLR_SP_MASK </td>
<td> - </td>
<td> y </td>
<td> writing 10 sets sp interrupt mask; <br>
	writing 01 clears sp interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:6] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5] </td>
<td> R DP_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns dp interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [4] </td>
<td> R PI_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns pi dma interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3] </td>
<td> R VI_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns vi interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [2] </td>
<td> R AI_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns ai interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1] </td>
<td> R SI_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns si interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> R SP_MASK </td>
<td> 0 </td>
<td> y </td>
<td> returns sp interrupt mask; </td>
</tr>


</table>

<a name="newregs">
<p>
<b><u> New MI Registers </u></b>
<p>
	All new MI registers control new functions and the security features.
	XXX
<p>
<table cellpadding=2 cellspacing=2 border=1>
<tr>
<td> Name </td>
<td> Address </td>
<td> Data </td>
<td> Read/Write </td>
<td> Reset </td>
<td> N64 </td>
<td> Description </td>
</tr>

<tr>
<td> MI_CTRL </td>
<td> 0x0430_0010 </td>
<td> [31:20] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> write data are ignored; <br>
	reads return 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [19] </td>
<td> RW UNMASK_IDE </td>
<td> 0 </td>
<td> n </td>
<td> 1 enables ide interrupt mask regardless of the setting
	in the MI_EMASK register;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [18] </td>
<td> RW SKI_PIF </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable secure kernel trap on writes to PIF RAM;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [17] </td>
<td> RW WEI_PIF </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable write error interrupt on writes to PIF RAM;
	reading MI_ER_INFO clears the interrupt;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [16] </td>
<td> RW BER_PIF </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable bus error on reads from PIF RAM in non-secure mode;
	0 reads return brom/bram data;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [15] </td>
<td> RW SKI_BNM </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable secure kernel trap on block writes
	(cacheable) to non-memory spaces;
	0 writes are ignored;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [14] </td>
<td> RW WEI_BNM </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable write error interrupt on block writes
	(cacheable) to non-memory spaces;
	0 writes are ignored;
	reading MI_ER_INFO clears the interrupt;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13] </td>
<td> RW BER_BNM </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable bus error on block reads
	(cacheable) from non-memory spaces;
	0 reads return undefined data;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [12] </td>
<td> WO SOFTRST </td>
<td> 0 </td>
<td> n </td>
<td> 1 cpu executes warm reset sequence;
	warm reset takes 64 sysclks;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11] </td>
<td> WO COLDRST </td>
<td> 0 </td>
<td> n </td>
<td> 1 change cpu divide mode;
	cpu executes cold reset sequence;
	cold reset takes 64k sysclks;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [10:8] </td>
<td> RW DIV_MODE </td>
<td> - </td>
<td> n </td>
<td> cpu pipeline clock multiplier; <br>
	000 = sysclk x 1; <br>
	001 = sysclk x 1.5; <br>
	010 = sysclk x 2; <br>
	011 = sysclk x 3; <br>
	all others are reserved; <br>
	set to 000 on pin reset; <br>
	not modified by internal resets; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7:0] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> write data are ignored; <br>
	reads return 0; <br>
</td>
</tr>

<tr>
<td> MI_SEC_MODE </td>
<td> 0x0430_0014 <br> non-secure mode </td>
<td> [31:0] </td>
<td> W </td>
<td> - </td>
<td> n </td>
<td> writes are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:0] </td>
<td> R </td>
<td> - </td>
<td> n </td>
<td> single reads arm the logic to enter secure mode and return 0;
	secure mode is entered during the issue phase of the next single
	read from address 0x1fc0_0000, valid boot vector data are returned
	for this fetch;
</td>
</tr>
<tr>
<td> </td>
<td> 0x0430_0014 <br> secure mode </td>
<td> [31:27] </td>
<td> RW </td>
<td> 0 </td>
<td> n </td>
<td> write data are ignored; <br>
	reads return 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [26] </td>
<td> RW SMD_EN </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable secure md trap; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [25] </td>
<td> RW SBUT_EN </td>
<td> 0 </td>
<td> n </td>
<td> 1 enable secure button trap; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [24] </td>
<td> RW IRAM_EN </td>
<td> 0 </td>
<td> n </td>
<td> iram accessibility; <br>
	1 in non-secure mode; <br>
	0 only in secure mode; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [23:8] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> write data are ignore; <br>
	reads return 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7] </td>
<td> RW SMD </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by md;
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [6] </td>
<td> RW SBUT </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by button;
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5] </td>
<td> RW STRAP </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by emulation trap;
	source is any of the SKI_* bits in MI_CTRL; <br>
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [4] </td>
<td> RW SFATAL </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by fatal pi error; <br>
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3] </td>
<td> RW STIMER </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by timer; <br>
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [2] </td>
<td> RW SAPP </td>
<td> 0 </td>
<td> n </td>
<td> 1 secure mode triggered by application; <br>
	NMI stays asserted as long as SMD, SBUT, STRAP, SFATAL, SAPP or STIMER are 1;
	must be written with 0 to re-enable nmi;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1] </td>
<td> RW RESET </td>
<td> 1 </td>
<td> n </td>
<td> brom/bram address space control; <br>
	set to 1 at reset; <br>
	1 brom 1fc0_0000, bram 1fc2_0000; <br>
	0 bram 1fc0_0000, brom 1fc2_0000; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> R SECURE </td>
<td> 1 </td>
<td> n </td>
<td> 1 if in secure mode; <br>
	writing 1 keeps secure mode on; <br>
	writing 0 leaves secure mode; <br>
</td>
</tr>

<tr>
<td> MI_SEC_TIMER </td>
<td> 0x0430_0018 <br> non-secure mode </td>
<td> [31:0] </td>
<td> RW </td>
<td> - </td>
<td> n </td>
<td> writes are ignored; <br>
	reads return 0; <br>
	the pre-scaler is used to divide the system clock before driving
	the counter timer; a value of n for the pre-scaler divides the system
	clock by n+1;
</td>
</tr>
<tr>
<td> </td>
<td> 0x0430_0018 <br> secure mode </td>
<td> [31:16] </td>
<td> W </td>
<td> 0 </td>
<td> n </td>
<td> writes set the pre-scaler; <br>
	writing 0 disables the secure timer;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:16] </td>
<td> R </td>
<td> x </td>
<td> n </td>
<td> current value of timer counter; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [15:0] </td>
<td> RW </td>
<td> x </td>
<td> n </td>
<td> timer start value; <br>
	the counter is loaded with start value, then decrements;
	upon reaching 0, the secure timer trap is triggered;
</td>
</tr>

<tr>
<td> MI_SEC_VTIME </td>
<td> 0x0430_001c <br> non-secure mode </td>
<td> [31:0] </td>
<td> RW </td>
<td> - </td>
<td> n </td>
<td> writes are ignored; <br>
	reads return 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> 0x0430_001c <br> secure mode </td>
<td> [31:17] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> reserved; <br>
	writes are ignored; <br>
	reads return 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [16] </td>
<td> RO </td>
<td> - </td>
<td> n </td>
<td> current state of time base clock; <br>
	restarts on new time base value;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [15:8] </td>
<td> RO </td>
<td> - </td>
<td> n </td>
<td> current count of time base divider; <br>
	loaded from time base value when 0; <br>
	counter decrements;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7:0] </td>
<td> RW </td>
<td> 62 </td>
<td> n </td>
<td> time base value; <br>
	divides sysclk, bit 0 forced to 0; <br>
	must be set to provide 1us time base;
</td>
</tr>

<tr>
<td> MI_ERR_ADDR </td>
<td> 0x0430_0020 </td>
<td> [31:0] </td>
<td> RO </td>
<td> x </td>
<td> n </td>
<td> captured address of first write error; </td>
</tr>

<tr>
<td> MI_ERR_DATA </td>
<td> 0x0430_0024 </td>
<td> [31:0] </td>
<td> RO </td>
<td> x </td>
<td> n </td>
<td> captured data of first single write error; </td>
</tr>

<tr>
<td> MI_ERR_INFO </td>
<td> 0x0430_0028 </td>
<td> [4] </td>
<td> RO WEVAL </td>
<td> 0 </td>
<td> n </td>
<td> 1 write error valid; <br>
	reading MI_ERR_INFO clears write error interrupt;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3] </td>
<td> RO WEMULT </td>
<td> x </td>
<td> n </td>
<td> 1 on multiple write errors before error info has been read;
	cleared on new capture of first error;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [2] </td>
<td> RO WEBLK </td>
<td> x </td>
<td> n </td>
<td> write error request type; <br>
	0=single, 1=block request
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1:0] </td>
<td> RO WESIZE </td>
<td> x </td>
<td> n </td>
<td> write error request size; <br>
	single: 00=1, 01=2, 10=3, 11=4 bytes <br>
	block: 00=8, 01=16, 10=32, 11=illegal bytes
</td>
</tr>

<tr>
<td> MI_RANDOM </td>
<td> 0x0430_002c </td>
<td> [31:1] </td>
<td> RO </td>
<td> x </td>
<td> n </td>
<td> writes are ignored; <br>
	reads return 0;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> RO </td>
<td> x </td>
<td> n </td>
<td> random number bit </td>
</tr>


<tr>
<td> MI_AVCTRL </td>
<td> 0x0430_0030 </td>
<td> [31:26] </td>
<td> RO </td>
<td> x </td>
<td> n </td>
<td> writes are ignored; <br>
reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [25] </td>
<td> RW <br> AV_RESET </td>
<td> 0 </td>
<td> n </td>
<td>
this bit controls reset on the AI and VI; <br>
writing 1 will take the AI and VI out of reset; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [24] </td>
<td> RW <br> PLL_BYPASS </td>
<td> 0 </td>
<td> n </td>
<td> writing 1 will bypass the video PLL;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [23] </td>
<td> RW <br> VENC_TEST </td>
<td> 0 </td>
<td> n </td>
<td>
writing 1 puts the video encoder into test mode; <br>
this can be used to reset the encoder; <br>
for simulations the encoder needs to be reset twice during startup <br>
to correctly put it into a known state; <br>
make VENC_TEST high for 4 clocks, wait 30 clocks, then <br>
make it high for another 4 clocks; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [22] </td>
<td> RW <br> VTRAP </td>
<td> 0 </td>
<td> n </td>
<td>
video encoder trap filter control;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [21] </td>
<td> RW <br> VMPAL  </td>
<td> 0 </td>
<td> n </td>
<td> writing 1 puts the encoder in MPAL mode;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [20] </td>
<td> RW <br> VNTPL </td>
<td> 1 </td>
<td> n </td>
<td> NTSC/PAL mode control; <br>
writing 1 puts the encoder in NTSC mode;
writing 0 puts the encoder in PAL mode;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [19] </td>
<td> RW <br> DAC_POWER </td>
<td> 0 </td>
<td> n </td>
<td> by default DAC is powered down; <br>
writing 1 powers up the video DAC;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [18:16] </td>
<td> RW <br> VPLL_PDIV </td>
<td> 0 </td>
<td> n </td>
<td> video PLL output divider P; <br>
this controls the relationship between output freq. <br>
and the VCO frequency; <br>
possible values are: <br>
0 -> FVCO <br>
1 -> FVCO/2 <br>
2 -> FVCO/4 <br>
3 -> FVCO/8 <br>
4 -> FVCO/16 <br>
</td>
</tr>

<tr>
<td> </td>
<td> </td>
<td> [15:9] </td>
<td> RW <br> VPLL_NDIV </td>
<td> 0 </td>
<td> n </td>
<td> video PLL input divider N; <br>
this divides the input clock; <br>
possible values are: <br>
0 -> Invalid <br>
1 -> 2 <br>
2 -> 3 <br>
... <br>
127 -> 128 <br>
</td>

<tr>
<td> </td>
<td> </td>
<td> [8:4] </td>
<td> RW <br> VPLL_MDIV </td>
<td> 0 </td>
<td> n </td>
<td> video PLL feedback divider M; <br>
this divides the feedback clock; <br>
possible values are: <br>
0 -> 1 <br>
1 -> 2 <br>
2 -> 3 <br>
... <br>
31 -> 32 <br>
</td>

<tr>
<td> </td>
<td> </td>
<td> [3:2] </td>
<td> RW <br> VPLL_FRANGE </td>
<td> 0 </td>
<td> n </td>
<td> video PLL VCO frequency range control; <br>
possible values are: <br>
0 -> 60 - 85 MHz <br>
1 -> 85 - 120 MHz <br>
2 -> 120 - 170 MHz <br>
3 -> 170 - 250 MHz <br>
this should be set such that the output frequency <br>
multiplied by VPLL_PDIV is in range <br>
</td>

<tr>
<td> </td>
<td> </td>
<td> [1] </td>
<td> RW <br> VPLL_DIVRESET </td>
<td> 1 </td>
<td> n </td>
<td> video PLL output divider reset; <br>
this should be set to 0 to use P divider;
</td>

<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> RW <br> VPLL_STANDBY </td>
<td> 1 </td>
<td> n </td>
<td> video PLL standby; <br>
setting this to 1 disables the PLL; <br>
this bit must be 1 for at least 30 uSec <br>
after programming all the values;
</td>
/<tr>

<tr>
<td> MI_EINTR </td>
<td> 0x0430_0038 </td>
<td> [31:0] </td>
<td> W </td>
<td> - </td>
<td> n </td>
<td> writes are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:26] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [25] </td>
<td> RO MD_STS </td>
<td> 1 </td>
<td> n </td>
<td> status of md input; <br>
	module 0=present, 1=removed; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [24] </td>
<td> RO BUT_STS </td>
<td> 1 </td>
<td> n </td>
<td> status of button input; <br>
	button 1=pressed, 0=released; <br>
	software has to wait for button release after power-on
	before enabling the pre-nmi trap;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [23:14] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13] </td>
<td> RW MD_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of md interrupt; <br>
	set by change in module presence; <br>
	cleared by writing this bit with 1; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [12] </td>
<td> RO BUT_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of button interrupt; <br>
	set and cleared by mi button logic; <br>
	interrupt is cleared by mask=0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11] </td>
<td> RO USB1_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of usb1 interrupt; <br>
	set and cleared by usb1 controller; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [10] </td>
<td> RO USB0_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of usb0 interrupt; <br>
	set and cleared by usb0 controller; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [9] </td>
<td> RO ERR_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of pi error interrupt; <br>
	set and cleared by pi; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [8] </td>
<td> RO IDE_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of pi ide interrupt; <br>
	set and cleared by pi ide controller; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7] </td>
<td> RO AES_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of pi aes interrupt; <br>
	set and cleared by pi aes controller; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [6] </td>
<td> RO FLASH_INTR </td>
<td> 0 </td>
<td> n </td>
<td> status of pi flash interrupt; <br>
	set and cleared by pi flash controller; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5:0] </td>
<td> RO </td>
<td> 0 </td>
<td> y </td>
<td> same as MI_INTR; </td>
</tr>

</tr>
<tr>
<td> MI_EMASK </td>
<td> 0x0430_003c </td>
<td> [31:28] </td>
<td> W </td>
<td> - </td>
<td> n </td>
<td> writes are ignored; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [27:26] </td>
<td> W <br> SET_MD_MASK <br> CLR_MD_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets md interrupt mask; <br>
	writing 01 clears md interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [25:24] </td>
<td> W <br> SET_BUT_MASK <br> CLR_BUT_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets button interrupt mask; <br>
	writing 01 clears button interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
	clearing the button mask disables the secure kernel
	button trap (pre_nmi);
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [23:22] </td>
<td> W <br> SET_USB1_MASK <br> CLR_USB1_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets usb1 interrupt mask; <br>
	writing 01 clears usb1 interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [21:20] </td>
<td> W <br> SET_USB0_MASK <br> CLR_USB0_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets usb0 interrupt mask; <br>
	writing 01 clears usb0 interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [19:18] </td>
<td> W <br> SET_ERR_MASK <br> CLR_ERR_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets pi error interrupt mask; <br>
	writing 01 clears pi error interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [17:16] </td>
<td> W <br> SET_IDE_MASK <br> CLR_IDE_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets pi ide interrupt mask; <br>
	writing 01 clears pi ide interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [15:14] </td>
<td> W <br> SET_AES_MASK <br> CLR_AES_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets pi aes interrupt mask; <br>
	writing 01 clears pi aes interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13:12] </td>
<td> W <br> SET_FLASH_MASK <br> CLR_FLASH_MASK </td>
<td> - </td>
<td> n </td>
<td> writing 10 sets pi flash interrupt mask; <br>
	writing 01 clears pi flash interrupt mask; <br>
	writing 00 or 11 leave mask unchanged; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11:0] </td>
<td> RW </td>
<td> - </td>
<td> y </td>
<td> same as MI_MASK </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31:14] </td>
<td> R </td>
<td> 0 </td>
<td> n </td>
<td> reads return 0; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13] </td>
<td> R MD_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns md interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [12] </td>
<td> R BUT_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns button interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [11] </td>
<td> R USB1_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns usb1 interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [10] </td>
<td> R USB0_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns usb0 interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [9] </td>
<td> R ERR_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns pi error interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [8] </td>
<td> R IDE_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns pi ide interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7] </td>
<td> R AES_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns pi aes interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [6] </td>
<td> R FLASH_MASK </td>
<td> 0 </td>
<td> n </td>
<td> returns pi flash interrupt mask; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [5:0] </td>
<td> R </td>
<td> 0 </td>
<td> y </td>
<td> same as MI_MASK; </td>
</tr>
</tr>

</table>

<a name="reset">
<p>
<b><u>Reset</u></b>
<p>
	The system supports 4 different types of reset: pin reset, cold reset,
	warm reset and bcp reset. Pin reset is generated externally to the chip and
	is input to the RST pin (active low). Cold and warm reset are generated inside
	the MI and routed to the 4300 CPU. In response to pin reset, the MI generates
	a cold reset to the CPU. The MI also ANDs all three active low reset lines
	together to form the bcp reset line, that is routed to the rest of the chip.
	So, the rest of the chip does not distinguish cold and warm rest. In addition
	to the bcp reset signal, the PI and the RI also get the pin reset signal,
	since they have special case behavior that depends on pin reset.
<p>
	The PI will latch the BoardID into the PI_GPIO register on pin reset
	(See the <a href="pi-spec.html">PI specification</a>). The RI clears the
	Refresh Rate register on pin reset. For bcp reset without power on reset
	the BoardID is not latched and the Refresh Enable bit is not cleared.
<p>
	To summarize the details of each of the reset.
<dl>
<dt><i>Pin Reset</i>
<dd>
	Pin reset is generated by keeping the RST line external to the chip low.
	Generally this happens on power-on. Pin reset will cause a cold reset to
	be generated to the CPU, and a bcp reset to the rest of the chip.
<p>
	On pin reset, all registers reset to their default values and the BoardID
	is latched into the top 16 bits of the PI_GPIO register. See the
	<a href="pi-spec.html">PI Specification</a>.
<p>
<dt>Cold Reset</i>
<dd>
	Cold reset is triggered by writing to the MI_CTRL register with a 1 in
	the COLDRST bit. This will also generate a bcp reset to the rest of the chip.
<p>
	On cold reset the DIV mode of the CPU is set from the bits programmed
	in the MI_CTRL register. With the exception of the DIV mode in the MI_CTRL
	register and the Refresh Rate register in the RI, all other registers are
	set to their default values on cold reset.
<p>
<dt><i>Warm Reset</i>
<dd>
	Warm reset is triggered by writing to the MI_CTRL register with a 1 in
	the WARMRST bit. This will also generate a bcp reset to the rest of the chip.
<p>
	On warm reset all registers with the exception of the DIV mode in the
	MI_CTRL and the Refresh Rate register in the RI are reset to their default
	values.
</dl>

<a name="intr">
<p>
<b><u>Interrupts</u></b>
<p>
	The 4300 supports 5 interrupt lines: INT0 - INT4.&nbsp;
<dl>
<dt><i>INT0</i>
<dd>
	INT0 is connected to the legacy RCP interrupt line, that muxes interrupts
	from the AI, VI, DP, SP, PI and SI. These status of the individual interrupt
	causes appear in the MI_INTR register. The interrupts can be masked using
	the MI_MASK register.
<p>
<dt><i>INT1</i>
<dd>
	INT1 is the BCP interrupt line and muxes the new interrupt sources introduced
	with new BCP functionality. These include: USB0, USB1, ERR, IDE, AES and FLASH.
	The latter four are all sourced from the PI unit (see <a href="pi-spec.html">
 	PI Specification</a>).&nbsp;
<p>
	The MI_EINTR register includes the interrupt status for these and the
	legacy interrupts, and the MI_EMASK can be used to mask/unmask these interrupts
	along with the legacy interrupts.
<p>
	The IDE interrupt mask is a special case. If the UNMASK_IDE bit is set
	in the MI_CTRL register, an IDE interrupt will trigger INT1, regardless of
	the state of the mask in the MI_EMASK register. This is to prevent applications
	from accidently disabling the interrupt, since it will be used for debugging.
<p>
<dt><i>INT2</i>
<dd>
	INT2 was used in the RCP as the Pre-NMI interrupt, and was connected to the
	Reset button on the console. In the BCP this line is directly connected to
	the Power/Reset button.
<p>
<dt><i>INT3</i>
<dd>
	INT3 is the MI_ERROR interrupt. It its triggered as a result of illegal
	writes to PIF RAM space, or illegal block writes to non-memory spaces, if
	this is enabled in the MI_CTRL register. The interrupt is cleared by reading
	the MI_ERR_INFO register.
<p>
<dt><i>INT4</i>
<dd>
	INT4 is unused.
</dl>

<p>
<b> Module Insertion/Removal Detection </b>
<p>
	The current status of the module presence can be read in the MD_STS bit of
	the MI_EINTR register. Module removal can trigger an interrupt or a secure
	kernel trap, if enabled. MD_INTR is set to indicate a change in the module
	status and stays active until cleared by writing 1. When servicing the
	exception, it is left up to software to debounce contact jitter during the
	module insertion or removal. Software can poll the MD_STS bit, possibly
	using software timers.

<a name="virage">
<p>
<b><u> Interface to Virage Non-Volatile Flash </u></b>
<p>
	Each of the virage blocks is addressed through a 64kB space in the
	MI boot space. This space is divided into four sub spaces which address
	the virage sram (Vx_MEM), the virage store controller (Vx_REG) registers,
	the mi virage control register (Vx_CTRL), the store controller execute
	space (Vx_NMS) and charge-pump execute space (Vx_CP). The MI_SEC_VTIME
	register is used to create a time base of 1us for the virage store
	controllers. The time base is not needed when the virage store controllers
	are bypassed. See the
<a href="nmsc-a5.doc">Virage Store Controller SPecification</a>
	for details.

<dl>
<dt> Vx_MEM
<dd> This is the shadow sram of the non-volatile array. <br>
	It supports single (uncached) and block (cached) accesses. <br>
	Reads accesses can be issued at any time. <br>
	Write accesses are blocked as long as the novea array is in keep mode. <br>
<p>
<dt> Vx_REG
<dd> The registers inside the virage store controller are accessed
	through this space. The store controler registers are 8 bits wide
	and use data bits [7:0].
	Only single (uncached) requests are supported. However, block
	(cached) requests are not trapped, do not cause errors and
	have undefined data behavior.
<p>
<dt> Vx_CTRL
<dd> This register controls how the charge pump and novea array are controlled.
	Only single (uncached) requests are supported. However, block
	(cached) requests are not trapped, do not cause errors and
	have undefined data behavior. <br>
	Bits [31] selects either the virage store controller or direct
	access by the cpu. <br>
	Bits [30:24] control the virage store controller. <br>
	Bits [23:0] bypass the virage store controller for direct cpu access. <br>
	Addr[13]=1: NMS executes command; <br>
	Addr[12]=1: charge pump CLKE is pulsed; <br>

</dl>

<table cellpadding=2 cellspacing=2 border=1>
<tr>
<td> V[012]_CTRL <br> V[012]_NMS <br> V[012]_CP </td>
<td> 0x1fc[89a]_cxxx <br> 0x1fc[89a]_exxx <br> 0x1fc[89a]_dxxx </td>
<td> [31:0] </td>
<td> RW </td>
<td> - </td>
<td> n </td>
<td> virage control register; <br>
	controls virage store controller; <br>
	cpu has direct control in bypass mode; <br>
	32-bit read/write access; <br>
	address must be 32-bit aligned; <br>
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [31] </td>
<td> RW NMS_BYP </td>
<td> 0 </td>
<td> n </td>
<td> store controller bypass; <br>
	NMS 0 = enabled, 1 = bypassed; <br>
	when bypassed, software has control over the
	CP_* and NV_* bits directly; the CP_* and NV_* bits
	reflect the current of the virage store controller
	when NMS_BYP is 0;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [30] </td>
<td> RO NMS_READY </td>
<td> - </td>
<td> n </td>
<td> store controller ready status; <br>
	0 = busy, 1 = ready;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [29] </td>
<td> RO NMS_PASS </td>
<td> - </td>
<td> n </td>
<td> store controller pass status; <br>
	0 = failed, 1 = pass;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [28] </td>
<td> RO NMS_KEEP </td>
<td> - </td>
<td> n </td>
<td> store controller keep status; <br>
	0 = normal, 1 = keep mode is on;
</td>
</tr>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [27] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> reserved; <br>
	writes are ignored, reads return 0;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [26:24] </td>
<td> RW NMS_CMD </td>
<td> 0 </td>
<td> n </td>
<td> store controller command; <br>
	000 = idle; <br>
	001 = serial sram access; <br>
	010 = full store; <br>
	011 = normal recall; <br>
	100 = normal compare; <br>
	101 = keep mode on; <br>
	110 = recall auto margin; <br>
	111 = reserved; <br>
	the command is started when address[13] is 1 and NMS_BYP is 0;
	address[13] can be on in the same access that sets NMS_CMD;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [23] </td>
<td> RO NV_RCREADY </td>
<td> - </td>
<td> n </td>
<td> novea recall ready status; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [22] </td>
<td> RO NV_MATCH </td>
<td> - </td>
<td> n </td>
<td> novea match status; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [21] </td>
<td> RW NV_RECALL </td>
<td> 0 </td>
<td> n </td>
<td> novea recall control; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [20] </td>
<td> RW NV_STORE </td>
<td> 0 </td>
<td> n </td>
<td> novea store control; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [18] </td>
<td> RW NV_COMP </td>
<td> 0 </td>
<td> n </td>
<td> novea comp control; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [17:16] </td>
<td> RW NV_MRCL </td>
<td> 00 </td>
<td> n </td>
<td> novea mrcl controls; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [15:14] </td>
<td> RW NV_TECC </td>
<td> 00 </td>
<td> n </td>
<td> novea tecc controls; </td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [13:12] </td>
<td> RW NV_BIAS </td>
<td> 00 </td>
<td> n </td>
<td> novea bias controls; </td>
</tr>

<tr>
<td> </td>
<td> </td>
<td> [11] </td>
<td> RW CP_RST </td>
<td> 0 </td>
<td> n </td>
<td> charge pump reset; <br>
	0 = operation, 1 = reset;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [10] </td>
<td> RW CP_PE </td>
<td> 0 </td>
<td> n </td>
<td> charge pump enabled; <br>
	0 = disabled, 1 = enabled;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [9] </td>
<td> RW CP_DATA </td>
<td> 0 </td>
<td> n </td>
<td> charge pump data bit; <br>
	bit stream for unlock sequence; <br>
	unlock is 10010110;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [8] </td>
<td> RW CP_VRANGE </td>
<td> 0 </td>
<td> n </td>
<td> charge pump vpp range; <br>
	see charge pump spec for details;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [7:4] </td>
<td> RW CP_VPPSEL </td>
<td> 0 </td>
<td> n </td>
<td> charge pump vpp select; <br>
	see charge pump spec for details;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [3:2] </td>
<td> RO </td>
<td> 0 </td>
<td> n </td>
<td> reserved; <br>
	writes are ignored, reads return 0;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [1] </td>
<td> RO CP_UNLOCK </td>
<td> - </td>
<td> n </td>
<td> charge pump unlock status; <br>
	0 = locked, 1 = unlocked;
</td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> [0] </td>
<td> RO CP_PORST </td>
<td> - </td>
<td> n </td>
<td> charge pump power-on reset; <br>
	0 = operational, 1 = reset;
</td>
</tr>
</tr>

<tr>
<td> V[012]_REG </td>
<td> 0x1fc[89a]_8xxx </td>
<td> [31:0] </td>
<td> RW </td>
<td> - </td>
<td> n </td>
<td> NMS register space; <br>
	32-bit read/write access; <br>
	address must be 32-bit aligned; <br>
	bits [7:0] are NMS register data; <br>
	bits [31:8] are ignored and read 0; <br>
</td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_8000 </td>
<td> [7:0] </td>
<td> RW </td>
<td> 0000_0001 </td>
<td> n </td>
<td> NMS CRSTO_0 register; </td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_8004 </td>
<td> [6:0] </td>
<td> RW </td>
<td> 0001_0010 </td>
<td> n </td>
<td> NMS CRSTO_1 register; </td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_8008 </td>
<td> [7:0] </td>
<td> RW </td>
<td> 1001_0000 </td>
<td> n </td>
<td> NMS CRM_0 register; </td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_800c </td>
<td> [7:0] </td>
<td> RW </td>
<td> 1001_0110 </td>
<td> n </td>
<td> NMS CRM_1 register; </td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_8010 </td>
<td> [7:0] </td>
<td> RW </td>
<td> 0101_1001 </td>
<td> n </td>
<td> NMS CRM_2 register; </td>
</tr>
<tr>
<td> </td>
<td> 0x1fc[89a]_8014 </td>
<td> [5:0] </td>
<td> RW </td>
<td> 0001_0101 </td>
<td> n </td>
<td> NMS CRM_3 register; </td>
</tr>

<tr>
<td> V[012]_MEM </td>
<td> 0x1fc[89a]_0000 <br> ... <br> 0x1fc[89a]_7fff </td>
<td> [31:0] </td>
<td> RW </td>
<td> - </td>
<td> n </td>
<td> virage sram space; <br>
	32-bit read/write access; <br>
	no byte write enables; <br>
	address must be 32-bit aligned; <br>
	smaller devices appear mirrored; <br>
</td>
</tr>

</table>

<p>
<b><u> TODO </u></b>
<p>
<ul>
<li> v2 crc
</ul>


<hr>
<font size="-1">
	Problems and comments to
<a href="mailto:berndt@broadon.com">
	berndt@broadon.com
</a>
</font>
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