proc-diffs.html
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<html>
<head>
<title>
Project BB Processor Differences
</title>
</head>
<body bgcolor="#ffffff" text="#000000"
link="#004868" vlink="#986424" alink="#00ffff">
<table width="100%" cellpadding=2 cellspacing=0 border=0>
<tr>
<td bgcolor="#e0e0e0">
Project BB Processor Differences
</td>
<td align=right bgcolor="#f0c0c0" width="20%">
<font color=red>
<b>Broad<i>On</i> confidential</b>
</font>
</td>
</tr>
</table>
<p>
<b> Various data sheets </b>
<p>
<dl>
<dd> <a href="vr4300-man.pdf">NEC Vr4300 User's Manual</a>
<dd> <a href="mips64-5kf-datasheet.pdf">MIPS64-5kf Data Sheet</a>
<dd> <a href="mips64-5kf-intguide.pdf">MIPS64-5kf Integrators Guide</a>
</dl>
<p>
<b> Changes in the processor interface </b>
<p>
The plan is to implement the processor as a hard- or soft core on chip,
The NEC Vr4300 processor will be replaced by an R4k core for a typical
single processor application (i.e. no hardware cache coherence). Below
is a list of items that require hardware and software changes.
<dl>
<dt> <b>SYSAD bus: parity, 32-bit versus 64-bit width</b>
<dd> The Vr4300 implements a 32-bit SYSAD bus without parity. Most r4k cores
implement a unidirectional interface for addresses, command and data. This
requires changes in the MIPS interface module (mi). The parity bits can be
hard-wired and checking of parity can be turned off by a SYSCMD bit on read
responses. Changing the rcp mi interface to 64 bits has minimal design
impact, compared to the SYSCMD changes below.
<p>
<dt> <b>SYSCMD bus: different command encodings</b>
<dd> The Vr4300 implements a reduced command bus interface. It is only 5 bits
wide, compared to the 9 bits of an r4k core. The command encoding must be
remapped because they are not an exact subset.
<p>
<dt> <b>EOK, RDRDY & WRRDY latencies</b>
<dd> The Vr4300 has the read and write ready signals combined into the EOK
(external agent ok) signal. The r4k cores have a separate read ready
(RDRDY) and write ready (WRRDY). In our implementation RDRDY and WRRDY
can be tied together. The EOK signal on the Vr4300 has a latency of
only one clock to the address issue cycle. However, the r4k RDRDY and
WRRDY signals have a latency of two clocks, which requires changes in
the mi state machines. It is likely that one clock will be lost, which
will be recovered by propagating the SYSAD interface to 64 bits in width.
<p>
<dt> <b>SYSAD bus arbitration</b>
<dd> The rcp does not arbitrate for the SYSAD bus, it is purely a slave.
The Vr4300 arbitration signal EREQ (external request) is tired to
inactive, PREQ (processor request) and PMASTER (processor is master)
are left unconnected. Similarly, the r4k bus arbitration signal EXTREQ
(external request) will be tied to inactive, and RELEASE (processor
released the bus) will be left unconnected.
<p>
<dt> <b>Other bus control signals</b>
<dd> The following signals map one-to-one (Vr4300 to r4k core):<br>
PVALID -> VALIDOUT, EVALID -> VALIDIN, INT[4:0] -> INT[4:0], NMI -> NMI
<p>
<dt> <b>Clocking</b>
<dd> No change, the rcp block will output MCLOCK at the frequency of the
SYSAD interface. The r4k clock PLLs align this clock internally just
as the Vr4300 does. The Vr4300 signals TClock, SyncOut, and SyncIn
have no equivalent on the r4k cores and did not interface with the rcp.
The supported bus clock frequencies will be 62.5MHz for compatibility
mode and 125MHz in native mode. Changing the cpu pipeline clock multiplier
requires a hard reset to resync the PLL.
<p>
<dt> <b>CPU initialization interface</b>
<dd> The Vr4300 has two speed control pins DIV[1:0] that were hard-wired
on the N64 board. The r4k cores implement a serial bit stream that is
read during cold reset (COLDRESET). The signals MODECLK and MODEIN
control the reading of these mode bits. Most of the bits will be
hard-wired, except for the pipeline clock multipliers. They will come
from a new register which controls compatibility modes and clock speeds.
Writing of this register will cause a cold reset and a cpu restart in
the new mode. The logic design for this new initialization block is
simple and depends to a great deal on the details of the chosen r4k core.
<p>
<dt> <b>JTAG and scan</b>
<dd> The rcp was developed without scan. However, for BB scan is required for
the manufacturing process and the programming of the internal flash. It
also helps greatly in lab debug. A small block of logic is required to
implement the security lockout feature which disables JTAG/scan, and
disables writes to the internal flash. See the security spec for more
details.
<p>
<dt> <b>Programmer visible differences</b>
<dd> The icache line size of 32 bytes is identical in the Vr4300 and the
r4k cores. However, the dcache line size of the r4k cores is 32 bytes
versus the 16 bytes of the Vr4300. Code using the CACHE instructions
for dealing with io coherence has to change.
The r4k cores allow a configurable number of TLB entries of 16, 32 or
48 compared to the 32 of the Vr4300. There are also differences in some
cp0 registers that deal with error conditions and debug. Floating point
code on the r4k cores will run faster at same clocks speeds because the
r4k core of interest implements a separate FPU.
</dl>
<hr>
<font size="-1">
Problems and comments to
<a href="mailto:berndt@broadon.com">
berndt@broadon.com
</a>
</font>
</body>
</html>