reset_int.html
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<html>
<head>
<title>Reset and Interrupt Generation</title>
<body>
<center>
<h1>Reset and Interrupt Generation</h1>
</center>
The goal of this document is to describe the BB reset and interrupt
handling, especially as it pertains to addressing the boot rom and it's
shadow boot SRAM. The high-level block diagram in Figure 1 describes
the reset generation mechanisms.
<h2>Boot ROM and SRAM addressing</h2>
The boot ROM (referred to as ROM in the Figure) memory space can be
mapped to either ROM or boot SRAM (BSRAM). Addresses used for writing,
ROMWrAddr, always map to BSRAM. The read address, ROMRdAddr, can either
map to ROM or BSRAM. This mapping is controlled by the system reset signal
_SysRst and PIO operations to MI register space. When _SysRst is asserted,
ROMRdAddr will address ROM. This will remain the case until a PIO is
issued to force ROMRdAddr to address BSRAM. System software can then control
the mapping of ROMRdAddr via PIO. Since the physical ROM size
is less than the size of the ROM address space, ROM addresses will alias
modulo the size of physical ROM.
<h2>Reset Signal Generation</h2>
The _SysRst signal can be generated by:
<ul>
<li> Power-on reset
<li> Button reset
<li> PIO to BCP register space
</ul>
The power-on reset is guaranteed to remain active for 100ms and is connected
to the hard reset input of the 4300 core. Power-on reset will cause an
assertion of _SysRst due to the OR logic used to create _SysRst.
<p>
The button reset feeds both a 0.5 second delay block and 4300 interrupt 2.
This is for backwards compatibility. The n64 reset button would trigger int
2 to allow the OS time for shutting down audio and video. A half second later
a reset would be generated. In our case, the delayed button reset is
extended to at least remain asserted for 64 processor clocks and feeds
the 4300 soft reset input. Do to the OR logic the 64 clock extended button
reset also generates _SysRst.
<p>
A PIO to the BCP can also cause a soft reset. When generated in this way
interrupt 2 on the processor is not affected, but otherwise the generation
of soft reset to the 4300 and _SysRst is identical to the button reset
previously described.
<p>
The output signal _IORst is intended to provide reset for the IO bus and
can be used for reseting other devices, such as audio. On the falling edge
of _SysRst, _IORst will become active (low). _IORst will remain active
until a register PIO issued from system software causes it to de-assert.
While _SysRst is not active, _IORst is in control of system software.
<h2>NMI and Reset vectors</h2>
The NMI, soft reset and hard reset all generate the same ROMRdAddr vector
referencing the beginning of ROM address space. An NMI can be generated by
either writing to a register in BCP address space, or having an internal timer
(controlled also be writing to a BCP register) fire. The boot process will
insure that NMI generated vector willalways address BSRAM, while the hardware
enforces that all vectors generated by reset address ROM.
<p align=center>
<IMG src="reset_int.png" align=center> <br>
<b>Figure 1.</b> Reset and Int Handling<br>
<h2>Other Interrups</h2>
It has previously been mentioned that int2 is used for button reset due to
backward compatibility constaints. The same holds true for int0, which will
be generated by the BCP in the same manner as the old RCP. New interrupts
used will be int1 and int3, and both these are generated by the BCP as well.
<p>
Int1 will be service new hardware, such as USB and IDE.
<p>
Int3 will be used for system errors such as store error (i.e., if an app
writes to an address is does not have access writes to), PI ECC and ATB
errors, and others.
</body>