BB_Player_Schedule.html 69.1 KB

Raw Blame History Permalink

<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>

  <meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
  <title>BB Player Schedule</title>
</head>
 <body>

<h1>BB Player Schedule</h1>
                This document is divided into two parts. The first part gives
  a  schedule     for major work items, the second describes the major work
  items  in more   detail,  with references to architecture and design documents.<br>
                <br>
                This document will be kept up to date to track progress.<br>

<h2><u>Schedule</u></h2>
                 The schedule below lays out the schedule for the BB player
 development       to Manufacturing Release. It covers BB SoC, BB Player system
 software,    BB   Player Development Kits and BB Player system hardware.
<br>
                <br>
                (Development Kit Release needs to be factored in)<br>
                <br>
                Major Milestones are:<br>

<ol>

  <li>June 3rd, Architecture Frozen, RCP verified.</li>

  <li>October 1st, All chip hardware design and implementation complete,
ready for first synthesis run at NEC.</li>

  <li>November 1st, RTL and Gate Level Verification complete, core system
 software       functionality prototyped and tested, Boot ROM code verified.</li>

  <li>January 15th, NEC Chip Tapeout.</li>

  <li>February 14th, Bring-up board design complete.&nbsp;</li>

  <li>February 28th, Engineering Samples of Chip come back from Fab. Bring-up
 diags complete. All BB Player software functionally complete and ready for
 bring up testing: Secure Kernel, DevKit Libs (compatibility, Filesystem,
USB, Security), Application Browser. Bring-up environment complete.<br>
     </li>

  <li>April 30th, Chip verified ready for mass production.<br>
                  </li>

  <li>May 30th, Manufacturing release for BB player, including system hardware,
        chip, tests (chip and system) and Software: Secure Kernel, and Application
 Browser.</li>

</ol>
                More detailed milestones and tasks are described below along
  with   current    status.<br>
                <br>
                <br>

<table cellpadding="2" cellspacing="2" border="1" width="100%">
                  <tbody>
                    <tr>
                      <td valign="Top"><b>Date/Milestones/Tasks</b><br>
                      </td>
                      <td valign="Top"><b>Status</b><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>June 3rd</b><br>


      <ol>


        <li>Architecture complete, all architectural specifications for functional
        blocks checked in, reviews complete.</li>


        <li>Verification of RCP using the Project Reality suites complete.</li>


      </ol>
                      </td>
                      <td valign="Top">1. Outstanding items on Architecture
 definition      are:<br>


      <ul>


        <li>Process, Embedded flash charactersitics</li>


        <li>CPU choice (MIPS or NEC)</li>


        <li>PI architecture (need to document flow including ECC, Decryption)</li>


      </ul>
                   <br>
             2. Outstanding items on RCP verification<br>


      <ul>


        <li>Confirm all DP test cases</li>


        <li>Run VI verification test cases<br>
                     </li>


      </ul>
                     </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>July&nbsp; 1st</b><br>
                 <br>

      <ol>


        <li>Finalize archictecture for PI, including data flow behavior through
      decryption and ECC, register definitions. (Frank, Pramila, Andy)</li>


        <li>Select AES decryption core (John, Frank, Pramila)</li>


        <li>Choose process, understand embedded flash characteristics (may
      impact design). (Wei)</li>


        <li>Choose CPU. (Wei)<br>
                     </li>


        <li> Kernel and Application Software development environment complete:
        compiler, simulator, debugger. (David, Andy)</li>


        <li>Enhance basic simulator to add internal flash/sram, external flash
(through PI - complete path may not be accurate) and secure mode switching.
      (Andy, Haishan)<br>
                     </li>


        <li>"IOSim" Verification environment, connecting to MI complete, including
memory and external device backdoors. (Haishan)</li>


        <li>Port the existing RCP verification suites over to BCP. (Haishan)<br>
                     </li>


        <li>DRAM design, implementation, test-bench, verification plan complete.
      (Doug)</li>


        <li>SI design, implementation, test-bench, verification plan complete.
      (Frank)</li>


        <li>Initial RTL behavioral of internal SRAM and internal Flash and
     secure mode registers. (Frank)<br>
                   </li>


        <li>First cut at Secure Kernel/Browser partitioning and functional
      definition and review. (Andy)</li>


        <li>First cut of Boot Code, Secure mode switching code. (David)<br>
                     </li>


      </ol>
                      </td>
                      <td valign="Top">1. Outstanding issues on architecture
  definition:<br>

      <ul>


        <li>MI design: SRAM, ROM, Flash, etc</li>

      </ul>
               <br>
        2. Outstanding issues in design:<br>

      <ul>


        <li>RI, x64 mode and obfuscation</li>


        <li>SI, serial port<br>
                </li>

      </ul>
               3. Outstanding issues in software:<br>

      <ul>


        <li>Need to finalize SK functional definition</li>


        <li>Boot code - can wait till next month<br>
                </li>

      </ul>
               4. Outstanding issues in SW development environment<br>

      <ul>


        <li>Simos simulation of PI, etc - can wait, connect to IOSIM first<br>
                </li>

      </ul>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>July 15th<br>
               <br>
               </b>

      <div>External vendors (John, Wei)</div>

      <div>

      <ol>


        <li>Sign license for AES with Cast</li>

      </ol>
               </div>

      <div>

      <div>Chip Design (Frank, Doug)</div>

      <div>

      <ol>


        <li>Clocking (internal clock generation/PLL/DLL specifications for
    NEC). Need to freeze first week of July.</li>


        <li>Architecture for MI, flash/sram/rom - need to  take account of
    debug/test for our bring up. This is required to provide Flash specifications
    for NEC. (Frank to do functional proposal and review, Doug will do details)</li>


        <li>RI functionally complete (remaining items are: 64 bit mode, Obfuscation).&nbsp;&nbsp;</li>


        <li>We need a proposal for DRAM Obfuscation (Frank, Pramila)</li>


        <li>SI functionally complete (remaining items are: Serial port, Connection
    to local controller through PI)</li>


        <li>Start MI middle of July</li>

      </ol>
               </div>


      <div>DV Infrastructure</div>


      <div>

      <ol>


        <li>Speed up IOSIM by keeping socket alive<br>
                 </li>


        <li>SIMOS connect to IOSIM (David)</li>

      </ol>
               </div>


      <div>DV Testing</div>


      <div>

      <ol>


        <li>All legacy RCP tests running (Haishan)</li>


        <li>RI test plan complete (Doug, Frank, Haishan)</li>


        <li>SI test plan complete  (Frank, Haishan)</li>

      </ol>
               </div>
               </div>

      <div>System Hardware (Bill)</div>

      <div>

      <ol>


        <li>Goal is to have an accurate BOM and to confirm  the specifications
    of the Chip</li>


        <li>Finalize all external interfaces: USB, SM, specifications  for
    our memory module</li>


        <li>Skeleton design, clocks, power supply, external  component selection</li>

      </ol>
               </div>

      <div>

      <div>System Software</div>


      <div>

      <ol>


        <li>Boot skeleton given new architecture:  Synchronize with hardware,
    make sure we have  backdoors for test/debug (Andy)</li>


        <li>Complete and detailed definition of all security functions and
    data structures (Pramila)<br>
                 </li>


        <li>Secure Kernel Framework: API mechanism, initial  API definitions,
    define key libraries. Need to do enough to define sizes for  SRAM/ROM,&nbsp;Flash
    (Andy mechanism/structure,  Pramila security routines).</li>

      </ol>
               </div>

      <div>Depot</div>

      <div>

      <ol>


        <li>First draft of protocols between depot and servers and  BB player
    (for download station): Activation, License purchase, content download.
  (Wilson)</li>


        <li>Rough schedule for HW and SW (need additional  resource) (Wilson,
    Bill, John)</li>

      </ol>
               </div>
               </div>
                      </td>
                      <td valign="Top"><br>
   External Vendors<br>

      <ul>

        <li>Cast license done</li>

      </ul>
         <br>
   Chip Design<br>

      <ul>

        <li>Internal clocking done, with the exception of DDR clocking scheme</li>

        <li>MI rough architecture done</li>

        <li>RI functionally complete. Obfuscation is not in, may be added
 later if schedule permits</li>

        <li>Proposal for DRAM obfuscation done</li>

        <li>SI complete to original specification. Design is to include rumble
 pak support which required extra logic. Serial port is not included.</li>

        <li>MI will not start till August.</li>

      </ul>
         <br>
   DV Infrastructure<br>

      <ul>

        <li>Speed up done.</li>

        <li>SIMOS connection TBD in August</li>

      </ul>
         <br>
   DV Testing<br>

      <ul>

        <li>All legacy tests are running with some failures on DP due to DDR
timing changes.</li>

        <li>RI initial test plan for module level done.</li>

        <li>SI initial test plan done.</li>

      </ul>
         <br>
   System Hardware<br>

      <ul>

        <li>Design guide for BB player done</li>

        <li>Initial rough design, including component selection done</li>

        <li>Initial BOM done</li>

      </ul>
         <br>
   System Software<br>

      <ul>

        <li>Boot is not complete, since MI is still in flux</li>

        <li>Security functions not yet defined, slipped till August</li>

        <li>SK API mechanism is defined. Sizes TBD in August.</li>

      </ul>
         <br>
   Depot<br>

      <ul>

        <li>Rough protocols done, but details TBD.</li>

        <li>Rough list of work items and effort estimate done. Need more detailed
functional spec to progress.<br>
           </li>

      </ul>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>August 5th</b><br>
                      <br>

      <div>External vendors (John, Wei)</div>

      <ol>

        <li>Letter of intent, with estimates from NEC.&nbsp;</li>

        <li>Get front-end libs/memory compilers (SRAM, rom) from NEC,  </li>

        <li>Get 4300 RTL model with test bench from NEC. </li>

        <li>Get Virage models/compilers.</li>

        <li>Select USB core (ARC or Mentor)</li>

        <li>Video encoder strategy.</li>

      </ol>
    Chip Design<br>

      <ol>


        <li>PI design, implementation, test-bench and verification plan complete
  (Frank).</li>

        <li>Debug strategy, including bring-up plan and any debug additions
  to the chip (Bill)</li>

        <li>Start BVCI/PVCI design for USB integration (Doug)</li>

        <li>Define Rumble Pak support architecture (Frank, Andy)<br>
            </li>


      </ol>

      <div></div>

      <div></div>

      <div><font face="Arial" size="2"></font></div>

      <div><font face="Arial" size="2"></font></div>

      <div><br>
         DV Testing<br>
               </div>

      <div>

      <ol>


        <li>Legacy RCP tests complete and passed on BCP (Haishan, Doug)<br>
            </li>

        <li>PI test plan, verification starts (Frank, Andy)</li>


        <li>SI test plan, system verification of functionality subset (doesn't
  include rumble pak) starts (Haishan)<br>
            </li>

      </ol>
               </div>

      <div>Development Kit/Compatibility  Libraries (David)</div>


      <div>

      <ol>


        <li>Final list of issues for compatibility: define  API's which need
    changing, define API's which can be stubbed and reduced size.  Other issues?&nbsp;</li>


        <li>Design for compatibility libraries complete.&nbsp;</li>


        <li>Ideas for automatically converting  ROMs.</li>

      </ol>
               </div>

      <div>System Software</div>

      <ol>


        <li>Initial implementation of all security functions, for sizing SRAM.
Include all components required for: activation, license acquisition, re-encryption,
playing (Pramila)</li>


        <li>Implementation of Boot code for ROM sizing (Andy)</li>


        <li>External Flash Filesystem definition complete (Andy)</li>

      </ol>
               <br>
                      </td>
                      <td valign="Top"><br>
   External Vendors<br>

      <ul>

        <li>Estimates from NEC done. LOI delayed.</li>

        <li>Complete design kit from NEC is available.</li>

        <li>4300 RTL is available.</li>

        <li>Virage models available.</li>

        <li>USB core selected. License agreement TBD.</li>

        <li>Video encoder strategy: Ricoh likely to supply netlist and we
 do logic remapping to NEC process.</li>

      </ul>
         <br>
   Chip Design<br>

      <ul>

        <li>PI Design complete.</li>

        <li>Debug strategy slipped by couple of weeks.</li>

        <li>USB slipped due to license delay</li>

        <li>Rumble Pak support requirements defined.</li>

      </ul>
         <br>
   DV testing<br>

      <ul>

        <li>Legacy tests are ported. Still outstanding bugs.</li>

        <li>PI verification will start (August 12th week)</li>

        <li>SI testing will start (August 12th week)</li>

      </ul>
         <br>
   Development Kit/Compatibility Libraries<br>

      <ul>

        <li>Initial investigation in progress. Final list to be done.&nbsp;</li>

        <li>Design ideas done</li>

        <li>ROM conversion has become lower priority.</li>

      </ul>
         <br>
   System Software<br>

      <ul>

        <li>Security libs rough implementation slipped by a month</li>

        <li>Boot code slipped due to MI slip. Goal is now end of August.</li>

        <li>Initial definition of file system done. Need to understand how
 this will be exported to applications through devkit</li>

      </ul>
         <br>
         <br>
                      </td>
                    </tr>
                    <tr>
            <td valign="Top"><b>August 15th</b><br>
            <br>

      <div>External vendors <br>

      <ol>

        <li>Finalize pricing range with NEC</li>

        <li>Sign USB license.<br>
            </li>

      </ol>
            </div>

      <div>
      <div>Chip Design<br>

      <ol>

        <li>Clock tree design, including DDR clocking strategy complete (Doug)</li>

        <li>Debug strategy, including bring-up plan and any debug additions
  to the chip (Bill)</li>

        <li>Definition of HW additions for Random Number generator<br>
          </li>

        <li>USB design, started.</li>

      </ol>
                    </div>

      <div>DV Infrastructure</div>

      <div>
      <ol>

        <li><font>SIMOS connected to IOSIM (David or Haishan?)</font></li>

        <li><font>Start USB verification sw porting (Haishan)<br>
             </font></li>

      </ol>
         </div>

      <div>DV Testing</div>

      <div>
      <ol>

        <li>High level software test plan. Define  what we need to run before
    tapeout. (SW Team)</li>

      </ol>
          </div>
            </div>

      <div>System Hardware<br>

      <ol>

        <li>Bring-up board rough definition, as part of debug (Bill)<br>
           </li>

      </ol>
         </div>

      <div>System Software<br>

      <ol>

        <li>Complete flow-chart, of secure operations (Pramila)<br>
           </li>

        <li>Initial estimate for BOOT rom size. (Andy, Pramila)<br>
           </li>

        <li>Initial estimates for Secure Kernel size (code size, data size)
 (Pramila, Andy)</li>

      </ol>
         </div>
            <br>

      <div>Development Kit/Compatibility  Libraries</div>
            <br>
            </td>
            <td valign="Top">External Vendors<br>
      <ul>
        <li>All done.</li>
        <li>Final contract with NEC TBD.</li>
      </ul>
      <br>
Chip Design<br>
      <ul>
        <li>Clocking finalized with NEC</li>
        <li>Debug/bring-up additions done</li>
        <li>HW random number generation logic defined</li>
        <li>USB not started till 9/17</li>
      </ul>
      <br>
DV Infrastructure<br>
      <ul>
        <li>Not done, awaiting 4300 port</li>
      </ul>
      <br>
DV Testing<br>
      <ul>
        <li>High level test plan TBD</li>
      </ul>
      <br>
System HW<br>
      <ul>
        <li>Initial pass done, needs review</li>
      </ul>
      <br>
System SW<br>
      <ul>
        <li>Flow chart done</li>
        <li>Boot size and SK size done</li>
      </ul>
      <br>
            </td>
          </tr>
          <tr>
                      <td valign="Top"><b>September 15th<br>
            <br>
            </b>
      <div>External vendors <br>

      <ol>

        <li>Development schedule agreed with NEC.</li>

        <li>Ricoh Video Encoder netlist transform started (?).<br>
           </li>

      </ol>
            </div>

      <div>
      <div>Chip Design&nbsp;</div>

      <ol>

        <li>MI design, implementation, test-bench and verification plan complete.
    MI includes secure SRAM, Virage Flash, ROM and secure mode registers (hardware
    protection, secure mode switching, etc). (Frank)</li>

        <li>System reset design, implementation, test plan complete. (Frank)</li>

        <li>USB core integration complete, test-bench verification plan complete
 (Doug)<br>
           </li>

        <li>Additional debug logic, including JTAG Controller design, implementation
  and verification plan complete. (Bill)</li>

        <li>Random Number Generator additions (Doug)<br>
           </li>

        <li>Clean-up of BCP done, including mapping all hand instantiations
  from old standard cell library, removing latches, removing tri-state busses.
  (Jeff)<br>
             </li>

        <li>Start creation of synthesis scripts to run DC, assume about 1
   week to clean up code, get it synthesizable. Start working at NEC for
first  synthesis pass. (Frank?)</li>

      </ol>

      <div>DV Infrastructure<br>
         </div>

      <div><font>&nbsp;</font></div>

      <div>DV Testing</div>

      <div>
      <ol>

        <li>USB testing code ported to IOSIM from ARC's testbench. USB verification
 starts (Haishan)</li>

        <li>MI, Secure mode, SRAM, Flash, ROM test plan verification starts
   (?)<br>
           </li>

        <li>Final system level test plan (eg reset testing, others?) (Frank,
    Doug)</li>

      </ol>
         </div>
         </div>

      <div>System Hardware&nbsp;</div>

      <div><br>

      <div>System Software</div>
            </div>

      <ol>

        <li>Core system software prototyped and tested.</li>

      </ol>

      <div>Development Kit/Compatibility  Libraries&nbsp;</div>
            <br>
                      </td>
                      <td valign="Top">External Vendors<br>
      <ul>
        <li>First cut development schedule discussed with NEC</li>
        <li>Ricoh technical eval complete, business negotiations done, awaiting
delivery</li>
      </ul>
      <br>
Chip Design<br>
      <ul>
        <li>MI design partially done, awaiting Virage Store controller, 4300
PLL porting</li>
        <li>USB core started on 9/17</li>
        <li>Debug logic defined, no resource to do it yet.</li>
        <li>Random number generator not done</li>
        <li>Hand instantiations, tri-states, latches still in progress, expecting
instantiations done by end of Sept.</li>
        <li>Synthesis script creation will start in early Oct.</li>
      </ul>
      <br>
DV Testing<br>
      <ul>
        <li>USB test code porting started, should be done by 9/25 for initial
connection tests.</li>
        <li>MI test plan development started</li>
      </ul>
      <br>
System Software<br>
      <ul>
        <li>Security libraries in progress, boot code integration started.</li>
      </ul>
      <br>
                      </td>
                    </tr>
                              <tr>
                      <td valign="Top"><b>October 1st<br>
            <br>
            </b>
      <div>External vendors<br>
            <br>
            </div>

      <div>
      <div>Chip Design<br>

      <ol>

        <li>Functionally complete.<br>
         </li>

      </ol>
       </div>

      <div>DV Infrastructure</div>

      <div><font>&nbsp;</font></div>

      <div>DV Testing</div>

      <div>
      <ol>

        <li> First pass behavioral verification tests complete. Review all
   test plans.</li>

      </ol>
         </div>
            </div>

      <div>System Hardware</div>

      <div>
      <ol>

        <li>Start ID development for BB enclosure, Break-out box</li>

      </ol>
            <br>

      <div>System Software</div>

      <div><font>&nbsp;<br>
            </font>
      <div>Development Kit/Compatibility  Libraries</div>
            <br>
            </div>
            </div>
            <br>

                  </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>October 21st<br>
            <br>
            </b>
      <div>External vendors<br>
            <br>
            </div>

      <div>
      <div>Chip Design </div>
                                   <br>

      <div>DV Infrastructure</div>

      <div><font>&nbsp;</font></div>

      <div>DV Testing<br>

      <ol>

        <li>Verification complete, hand-off final netlist to NEC.<br>
           </li>

      </ol>
         </div>

      <div><font>&nbsp;</font></div>
            </div>

      <div>System Hardware</div>

      <ol>

        <li>ID for BB enclosure, Break-out box complete.</li>

      </ol>
            <br>

      <div>System Software<br>

      <ol>

        <li>BOOT code complete and verified.<br>
           </li>

        <li>Core system software (Secure Kernel and Devkit) verified.<br>
           </li>

      </ol>
         </div>

      <div><br>
      Development Kit/Compatibility  Libraries</div>
            <br>
            <br>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>November 4th</b><br>

                                 <br>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>November 15th</b><br>


      <ol>


        <li>Mechanical design for BB enclosure, Break-out box complete.</li>


        <li>Start hard tool development.</li>


      </ol>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>December 2nd</b><br>

                                 <br>
         </td>
         <td valign="Top"><br>
         </td>
       </tr>
       <tr>
         <td valign="Top"><b>December 20th</b><br>
                <br>
         </td>
         <td valign="Top"><br>
         </td>
       </tr>
       <tr>
                      <td valign="Top"><b>January 15th</b><br>
       <br>


      <ol>

        <li>Tape-out from NEC</li>

      </ol>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>February 3rd</b><br>

                                 <br>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>February 14th</b><br>


      <ol>


        <li>Bring-up board design complete. Start build, set up lab.</li>

        <li>Hard tool for enclosures complete</li>


      </ol>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
                      <td valign="Top"><b>February 28th</b><br>


      <ol>


        <li>Engineering Samples of Chip.</li>

        <li>System tests/diags.</li>

        <li>Bring-up tools/development environment complete.<br>
           </li>

        <li>System software: Secure Kernel, DevKit libs, Application Browser
 complete and tested in simulation environment.</li>


      </ol>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
                    <tr>
         <td valign="Top"><b>March 31st</b><br>

      <ol>

        <li>Chip and system design verified</li>

        <li>Secure Kernel software complete</li>

        <li>Supply developers with units for final release game testing, or
development if necessary.</li>

      </ol>
         </td>
         <td valign="Top"><br>
         </td>
       </tr>
       <tr>
                      <td valign="Top"><b>April 30th<br>
                      <br>
                      </b>Chip Ready for Production.<br>


      <ol>


        <li>Chip, Boot ROM, Secure Kernel verified and ready for mass production.</li>

        <li>Chip scan tests, Packaged part tests, Security information insertion
 done.<br>
           </li>


      </ol>
                      </td>
                      <td valign="Top"><br>
                      </td>
                    </tr>
       <tr>
         <td valign="Top"><b>May 30th</b><b><br>
         </b><br>
   Manufacturing Release for System and Software.<br>
         <br>

      <ol>

        <li>Browser application done.<br>
           </li>

        <li>Manufacturing tests for system (Go-No-Go) done.<br>
           </li>

        <li>System in production.</li>

      </ol>
         <br>
         </td>
         <td valign="Top"><br>
         </td>
       </tr>

  </tbody>
</table>
                <br>
 <br>

<h2><u>NEC Schedule</u></h2>
 The major items from NEC back-end schedule are as follows:<br>

<ol>

  <li>Synthesis, including timing analysis, BroadOn do gate-level verification,
ending in clean run: 4 weeks</li>

  <li>Synthesis is overlapped with Floor-planning.<br>
   </li>

  <li>Scan insertion, BIST insertion: 1 week</li>

  <li>Place and Route: 6-8 weeks</li>

  <li>Tape-out to engineering samples (ES): 5 - 8 weeks</li>

  <li>BroadOn evaluation of ES: 4 weeks</li>

  <li>Quality testing, assume 2000 hours: 2-4 months (this is conservative)</li>

  <li>Time to get to mass production: 2-4 months (this is very conservative)</li>

</ol>
 Mass production trigger can overlap quality testing with Risk order.<br>
 <br>

<h2><u>Major Work Categories</u></h2>

<h3>BB Chip Design and Implementation</h3>
                BB SoC is based around N64 RCP, with an integrated MIPS R5K
 core,    plus   numerous  integrated IP blocks. Our primary goal is to achieve
 backwards     compatibility  for N64 titles with minimal porting in the lowest
 cost platform,    while at  the same time providing and end-point for secure
 electronic delivery    and a secure execution environment.<br>
                <br>
                The main work items are:<br>

<ol>

  <li>Develop the architecture and algorithms. See <a href="http://intwww/bb/rf/doc/hw/index.html">
                Architecture Documentation</a>
                 for details.</li>

  <li>Design&nbsp; of new functional blocks . The major blocks are:</li>

</ol>

<blockquote>
  <ul>


    <li>Change memory sub-system to DDR.</li>


    <li>Integrate PIF/Controller functionality into SI/PI, Add a serial interface
        to SI for Modem and debugging.</li>


    <li>Change MIPS interface to uni-directional 64 bit SysAD.</li>


    <li>Add internal flash and SRAM and secure kernel switching to MIPS interface.<br>
                    </li>


    <li>Add NAND Flash, Smart Media interface to PI/host bus.</li>


    <li>Add decryption engine and Flash block mapping hardware to fast, contiguous
        access to encrypted data for applications.<br>
                    </li>


    <li>Add LCD controller interface to PI/host bus.</li>


    <li>Add Ethernet MAC to C/D bus (possibly add Phy).<br>
                    </li>

  </ul>
                  </blockquote>

  <ol start="3">


    <li>Selection of 3rd party IP (We need a detailed list with specs  for
       things like SRAMs, PLLs, DLLs, etc):&nbsp;</li>

  </ol>

  <blockquote>

    <ul>


      <li>Standard Cells.</li>


      <li>Memories: ROM (divider),&nbsp; SRAMs (isram, TMEM, IMEM, DMEM),
        Embedded Flash.&nbsp;</li>


      <li>CPU: MIPS R5Kf.</li>


      <li>Soft core logic: Ethernet MAC, AES, Serial port.</li>


      <li>Analog IP: DLL/PLL, SSTL2 drivers, (we may also integrate Ethernet
        Phy, Audio/Video DACS). NurLogic is a recommended analog IP vendor
 for    TSMC.   Mysticom has Ethernet Phy.</li>


    </ul>
                    </blockquote>


    <ol start="4">


      <li>Implementation of functionality and integration into system.</li>


      <li>Synthesis, Scan Insertion, Timing validation, P&amp;R, tapeout.
        The current plan is to use consultants to help us with this phase.
 Potential       options are: Reshape, Nova (?).</li>


      <li>Package choice/design (consultant). ASE is a potential provider
        for this service.</li>


      <li>Chip test development, including probe card and test program (consultant).</li>


    </ol>


    <h3>BB Chip Verification</h3>
                 The plan is to use the system software team to support the
 verification       effort, since it will not be possible to meet schedule
 otherwise. In  the    current plan verification looks like one of the critical
 path items.  Verification     is complicated by the fact that we are integrating
 IP from  Nintendo which     was never intended to be used as a core and so
 the supplied  verification    environment is messy and inconsistent.<br>
                    <br>
                We have the complete source tree which comes from SGI and
there    are   several   verification environments. IOSIM, which is primarily
used    to verify   the IO  portions (MI, SI, AI, VI, PI, RI), RSP which is
used   to validate  the programmable  signal processor, RDP which is used
to validate    the display   processor, along  with individual module tests
in verilog.   The current plan   is to bring up and use IOSIM and the RSP
environments,   then move these over   to be used in BB chip verification.
For the RDP we   may use the verification   environment, or the set of tests
that were developed    for test vector generation,   since the RDP verification
environment is  very  convoluted and we may have   problems getting it up.<br>
                    <br>
                The major tasks are:<br>


    <ol>


      <li>Validation of RCP netlist with NEC GDS. To make sure we have the
        final code that was used to make the RCP we will generate a netlist
  from     this code and formally verify against the netlist/GDS used by
NEC   to fab    the chip. We need consultants help here to generate the netlist.</li>


      <li>Bring-up RCP verification and validate RCP functionality.</li>


      <li>Block level verification and directed testing. The plan is each
        designer will put together a test-bench which is verilog based, use
  C/D    bus  stubs, so that directed testing of their block can be done.</li>


      <li>"IOSim" environment. We will put together an environment consisting
        of the BCP without the MIPS core, similar to IOSim for RCP. This
allows       us  faster simulation times and more control over the events
that are   triggered,      since we are not restricted by having the CPU.
The enhancements   needed   from   current IOSim are:</li>


    </ol>


    <blockquote>

      <ul>


        <li>Memory backdoors</li>


        <li>Access to external peripheral IOs,&nbsp;</li>


        <li>Parallelize IO operations (allow stimulation of external peripherals
        simultaneously with SysAD transactions).</li>


      </ul>
                      </blockquote>


      <ol start="5">


        <li>Complete system verification, including CPU. This environment
        will allow us to run system level tests, including fragments of our
  system      software, such as boot code, secure kernel switching, etc.</li>


        <li>Port the RSP, IOSim and RDP tests to the BB environments.</li>


        <li>Add new tests for new functionality, add tests to RCP legacy
to cover more cases.</li>


      </ol>
       The basic steps in DV for each module and system are:<br>

      <ol>

        <li>Develop a test plan, which includes functions that need to be
   covered, DV environment requirements: eg verilog level tests, IOSIM level
   test, DV environment enhancements required, how to run the tests. The test
   plan should be enhanced as test development proceeds to include the test
  list.</li>

        <li>Module designer is responsible for covering a reasonable set of
functionality from the test plan, through low-level verilog based tests.</li>

        <li>For most blocks there will be System level tests written in the
   IOSIM environment which complement the module verilog based tests.</li>

        <li>Software folks will also prepare a set of system function tests
   that cover the main ways in which the hardware will be used.</li>

        <li>Test plans will be reviewed by several people once they are done
   and again before tape-out so we can sign-off.</li>

      </ol>
             <br>

      <h3>BB Player System Hardware</h3>
                We will have two types of system hardware: Our bring-up board,
   which    will   be become the Development system, and the final production
   board  and  system.<br>
                      <br>
                      <b>Bring-up/DevKit Hardware Development</b><b><br>
                      </b><br>
                 For the Development system the assumption is we only need
 small    quantities.    The plan is to use a standard PCI form factor board.
 The  system  uses PCI   only for power and has external serial port (using
 the  on chip  serial port)   and Ethernet which can be looped back into
the  PC  for debugging.  The state   of the on-chip Flash may be different
&nbsp;than   for production  chips, since    we may leave the embedded  Flash
programmable,   or put in different code.<br>


      <ol>


        <li>Board design (2 weeks).</li>


        <li>Fabricate and build enough boards for bring-up (2 weeks).</li>


      </ol>
                     <br>
                      <b>Production BB Player system hardware, break-out
box,   cables,     flash  expansion modules</b><b>, packaging, etc<br>
                      <br>
                      </b>The production BB player will be manufactured in
 quantities      of  millions and needs hard tool for enclosures, pass reliability
 and  FCC    qualification,  etc. Full details are TBD, but rough tasks and
 times  for   scheduling are as  follows:<br>


      <ol>


        <li>ID - conceptual design of plastics (4 weeks)</li>


        <li>Production board design (1 week)</li>


        <li>Mechanical design (4 weeks)</li>


        <li>Diagnostics for Bring-up and Manufacturing tests (leverage verification
        suites, 2 weeks?).<br>
                        </li>


        <li>Board test fixture development (2 weeks)</li>


        <li>Hard tool development (8 weeks to build a hard tool)</li>


        <li>Reliability and qualifications (5-6 weeks for reliability, quality,
        final sw QA, ICT tweaks, uses DVT build)</li>


        <li>Final PVT (1-2 weeks)</li>


      </ol>


      <h3>BB Player Software Development Environment (pre-chip)</h3>
               The plan is to have system software and development kits (see
  below    for   information) completely done and ready for testing when
the   chip comes   back.   To do this we will develop a complete simulation
environment   for  the BB chip  and system. The simulation environment is
based around        <a href="http://simos.stanford.edu">         SimOS </a>
                from Stanford, with simulation models for our specific devices
   added.    The  hardware component models will be functionally accurate
with   some notion   of timing (accuracy TBD).<br>
                     <br>
               In addition to the simulator we will put together from available
   sources     a Compiler, linker and Debugger. The code and also the debugger
   will work     directly on the final hardware.<br>


      <h3>BB Player System Software</h3>
               The BB player system software is divided into:<br>


      <ol>


        <li>Secure kernel, which provides boot code, all the security functions,
       and presents a set of system calls to applications. Final set of system
     calls  is TBD.&nbsp;</li>


        <li> Application browser, which is the application launched on reset
       and when exiting from a game. It provides a user interface to allow
 browsing      and management of available applications/content.</li>


      </ol>
               Details of these components and the partitioning of functionality
    between    them are given in the <a href="http://therouter.routefree.com/bb/rf/doc/BB_Game_System_SW_Architecture_Overview.htm">
              Player Software Architecture</a>
               document.<br>
                     <br>
               The complete Secure Kernel and Browser will be developed before
   the   chip   comes back using the simulation environment described above.
   In addition,     we will run key pieces of the kernel and application
code    on the verilog    RTL behavioral simulation of the complete system.<br>


      <h3>BB Player Application Porting and Development Kits</h3>
               Applications written for N64 use a collection of libraries
originated      by  SGI and extended and maintained by Nintendo. These libraries
provide     a basic  embedded OS, device IO, graphics and audio functionality.
As a  result   of changes to the underlying hardware in the BB player, some
 of these libraries   will need to change. For a list of the software impacts
  of hardware changes   see       <a href="http://intwww/bb/rf/doc/hwimpact.html">
      Porting Issues</a>
               . <br>
                     <br>
              The current plan for porting games to overlap the schedule
with   system    development  is to provide a software porting kit that can
be used  with  the  N64 development  environment, that will allow localization
to proceed.  Once  the BB Player hardware is available the final game development
 and testing  can take place.       <br>
                    <br>
              In addition to supporting the N64 dev kit functions we will
introduce      a  simplified development environment for 2D and 3D graphics
to allow  rapid    development of BB player specific games. The features of
this are  TBD, but   currently the plan is it should be layered on top of
the current  N64 dev  kit API's to isolate the developer from some hardware
details.<br>
                    <br>
              The final dev kit released will include security mechanisms
to  support     electronic  publishing of applications through the BB server
 infrastructure.     See <a href="http://intwww/bb/rf/doc/BB_Servers/bbserver_arch.html">
     BB   Server Architecture Document</a>
              .<br>


      <h3>Game Porting/Testing for Release</h3>
              The basic development flow for Game Porting needs to be developed
   in  collaboration   with Publishers. There is likely to be some sensitivity
    to  release source   code, so the plan is to try to wherever possible
solve    porting  problems by  providing new libraries compatible with the
existing    onces that  can be relinked,  provide tools that developers could
run to   make changes  to game code and partition code required for localization
 to  require the release of some minimal subset of actual source.<br>
                    <br>
                    <br>


      </body>
      </html>