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<title>AES resources</title>
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</head>

<body lang=EN-US link=blue vlink=purple style='tab-interval:.5in'>

<div class=Section1>

<h2>Chip Level Support for Security</h2>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>The three basic problems to solve are </p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l18 level1 lfo3;tab-stops:list .5in'><b>Authentication
     of flash</b> inserted with a game to be played on our chip. The game
     should come from our depot and correspond to a license issued by us.</li>
 <li class=MsoNormal style='mso-list:l18 level1 lfo3;tab-stops:list .5in'><b>Authentication
     of game running from DDR (secure execution)</b>. This is to prevent
     someone from attaching an auxiliary board to interface with our chip, with
     DDR and flash/cartridge interface to run their own games that did not come
     from our servers. Or somehow replace data in our DDR after it is
     downloaded from flash.</li>
 <li class=MsoNormal style='mso-list:l18 level1 lfo3;tab-stops:list .5in'><b>Encryption</b>:
     since we do not have the resources (latency, performance) to do AES
     encryption and decryption in and out of DDR, we decrypt content in the
     chip and write out to DDR<span style="mso-spacerun: yes">  </span>in
     plaintext form. The game executes out of there, exposing plaintext again.
     Though all data traffic to DDR cannot be secured, we attempt to secure
     critical code/data.</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>The first problem has to be solved because it is fundamental
to our revenue model. Also it is a mass produce-able break-in. The second and third
have to be solved for preventing long term compromise of the content
distribution chain.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Resources:<o:p></o:p></b></p>

<p class=MsoNormal>The resources on the chip at our disposal to solve the above
problems are </p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l6 level1 lfo6;tab-stops:list .5in'>Chip
     level support for a secure mode with access to restricted devices/registers.</li>
</ul>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l5 level1 lfo9;tab-stops:list .5in'>An
     internal flash that can only be accessed in secure mode to store secure
     data.</li>
 <li class=MsoNormal style='mso-list:l5 level1 lfo9;tab-stops:list .5in'>Limited
     number of cycles in secure mode available at regular timed intervals
     (non-maskable) to do some monitoring/execution of security checks.</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>We address the three problems in the order of importance:</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Problem 1:</b></p>

<p class=MsoNormal><b>Authentication of flash: (current final)<o:p></o:p></b></p>

<p class=MsoNormal>(Other proposals for flash authentication are summarized in
the document Proposals for authenticating content in BB player. Unless some
problem is discovered, the method outlined here will supersede those).</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>The usage model</b>: The user takes the removable memory
module in to the depot to download content (and license) into it. He brings it
home and attaches it back to the player to play the games on it.<span
style="mso-spacerun: yes">  </span>(An alternate model to download content was
to take the BB player to the depot and download via the Ethernet. Arguments
discussing the two approaches are in the following document: Analyzing
Security for new Usage Model. Review the summary at the end of that document for
justification for the new model).</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>The license and the content are delivered to the BB player
at possibly different times, through different connections, when the removable
memory module is connected to the depot. The content is possibly cached in the
depot, but the license has to be issued by the server each time, when paid for
by a customer. </p>

<p class=MsoNormal>To mention the relevant parts of the license:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l3 level1 lfo12;tab-stops:list .5in'>Content
     encryption key</li>
 <li class=MsoNormal style='mso-list:l3 level1 lfo12;tab-stops:list .5in'>MD5
     hash of the entire content </li>
 <li class=MsoNormal style='mso-list:l3 level1 lfo12;tab-stops:list .5in'>A
     random number/seed/key for BB re-encryption</li>
 <li class=MsoNormal style='mso-list:l3 level1 lfo12;tab-stops:list .5in'>This
     package is signed, certified by server and encrypted using the BB public
     key</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Outline:<o:p></o:p></b></p>

<p class=MsoNormal>The following are the steps that achieve the authentication
of content transferring from depot to chip for game play: (In the following
discussion the function of the depot can be replaced by a smart media card
which has the copy of content and license downloaded from the depot) <b>(Follow
the violet solid path for content in the figure below)<o:p></o:p></b></p>

<p class=MsoNormal style='margin-left:.25in'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     license for acquiring content has been paid for and acquired on the memory
     module.</li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The content
     is downloaded to the memory module in its original encrypted format as it
     is stored in the depot.</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'>(The following operations happen
in secure mode in the player)</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     content key is extracted from the license. </li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     BB player generates a new key by mixing in randomness to the re-encryption
     key in the license. (see details later).</li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     content (which has been encrypted by this key by the server) is downloaded
     from the memory module.</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'><b>(Step 1 in figure)<o:p></o:p></b></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>Every
     N (multiple of 128 bit) byte block is decrypted (AES), and a MD5 hash is
     computed. The state of the hash calculation is saved. </li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     N byte block is re-encrypted (AES software) using the new key and stored
     in external flash. (see details later for mode and hardware). <b>(Step 2
     in figure)</b></li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>Every
     time a new block is downloaded the hash calculation continues as if it
     were a continuous stream of data</li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>All
     the content data is downloaded and saved in external module in this
     manner. (Possibly overwriting the original data). <b>(Step 3 in figure)<o:p></o:p></b></li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     computed hash is verified against the signed hash in the license. If true,
     the new key is saved in internal flash and the application is allowed to
     run.</li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     application runs by decrypting flash content in run time while DMA occurs
     from flash to DDR, storing decrypted content in DDR. The key set up is
     done in secure mode and decryption in hardware.</li>
 <li class=MsoNormal style='mso-list:l19 level1 lfo15;tab-stops:list .5in'>The
     control exits secure mode after setting up the keys etc. and passes
     control to the application.</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<h1>Memory card usage for storage/transport of content/license (blue dashed and
green dotted paths in diagram below):</h1>

<p class=MsoNormal>We limit the internal flash to only store as many (cid, key)
pairs as the memory modules can hold content. If additional storage is needed,
the smart media cards can be used for content backup. Smart media card can be
used for storage of content at home or for transporting from the depot. The
following operations are done:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l4 level1 lfo19;tab-stops:list .5in'>When
     content is stored back into the smart media card from the memory module it
     is decrypted by the internal key and re-encrypted by the original content
     key (in license) and stored in smart media card <b>(follow blue dashed
     path in the diagram). </b>The internal flash entry (cid, key) is deleted.</li>
 <li class=MsoNormal style='mso-list:l4 level1 lfo19;tab-stops:list .5in'>When
     content is loaded from smart media card (in either case) it is decrypted
     by content key and re-encrypted by a newly generated key on the way to
     flash (in the standard memory module).<span style="mso-spacerun: yes">
     </span><b>(follow green dotted path in the diagram)<o:p></o:p></b></li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Justification of approach</b>: Our chip can only play
content for which internal re-encryption key is available in flash. Since the
data is re-encrypted using a new key and stored in flash during download;
during run time, an illegal flash cannot masquerade as a legal one and play on
our chip, since the chip internally stores this new key. <b>This new key never
leaves the chip, and is known only to that BB. </b>So if someone replaces the
flash or replaces content at any time, the content would not run on our chip.
Secondly, this approach requires no hardware support (see details).</p>

<p class=MsoNormal>Other approaches that involve run time checking of hashes of
data read from flash require porting effort or a lot of state storage in the
chip.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

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style='mso-ignore:vglayout;position:absolute;z-index:2;margin-left:367px;
margin-top:581px;width:39px;height:39px'>

<table cellpadding=0 cellspacing=0>
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  <td width=39 height=39 align=left valign=top bgcolor=white style='border:
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  style='position:absolute;z-index:4'>
  <table cellpadding=0 cellspacing=0 width="100%">
   <tr>
    <td><![endif]>
    <div v:shape="_x0000_s1114" style='padding:3.6pt 7.2pt 3.6pt 7.2pt'
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  <td width=39 height=27 align=left valign=top bgcolor=white style='border:
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<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>The following shows the path during playback. The black
arrows are re-encrypted content, blue arrows are decrypted plaintext content.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b><!--[if gte vml 1]><v:shape id="_x0000_i1026" type="#_x0000_t75"
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</v:shape><![endif]--><![if !vml]><img width=589 height=253
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<p class=MsoNormal><b><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></b></p>

<p class=MsoNormal><b>Details:<o:p></o:p></b></p>

<p class=MsoNormal><b>AES software or hardware:<o:p></o:p></b></p>

<p class=MsoNormal><b>Software:<o:p></o:p></b></p>

<p class=MsoNormal>AES encryption key setup: 300 clocks</p>

<p class=MsoNormal>AES decryption key setup:<span style="mso-spacerun: yes">
</span>1400 clocks</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>For a large body of data, its about 20 cycles per byte for
encryption/decryption.</p>

<p class=MsoNormal>Requires about 60 bytes of RAM, about 1K bytes of code for
encryption and 1K for decryption.</p>

<p class=MsoNormal>Key storage: 16 bytes</p>

<p class=MsoNormal>On the fly sub-key generation:<span style="mso-spacerun:
yes">  </span>only 36 bytes of RAM</p>

<p class=MsoNormal>Precomputed subkeys: 160 bytes storage, faster execution.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>On a 100Mhz processor, (just for lower bounding), it takes
about 0.2 s per Mbyte. Which is less than the flash writing speed of 1-2 s/MB.
So the encryption can be done in software.</p>

<p class=MsoNormal>The decryption hardware already is designed in because it
has to be done in real time for DMA access from flash, hence it could be used
for decryption during content loading to flash as well.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>We need to use CBC mode while encrypting to make it less
vulnerable to code book style attack, so reading becomes slightly inefficient
(1 previous block needed to decrypt current block).</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Hardware</b>: </p>

<p class=MsoNormal>Hardware speed depends on size of the core. (the appendix
has list of core vendors).</p>

<p class=MsoNormal>Example, using 128 bit key length,<span style="mso-spacerun:
yes">  </span>(one operation is 128 bits.). (at 200MHz, 0.18 micron tech)</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l1 level1 lfo22;tab-stops:list .5in'>20 K
     gates, 44 cycles/operation, 500 Mbits/sec</li>
 <li class=MsoNormal style='mso-list:l1 level1 lfo22;tab-stops:list .5in'>34 K
     gates, 11 cycles/operation, 2.3 Gbits/sec</li>
 <li class=MsoNormal style='mso-list:l1 level1 lfo22;tab-stops:list .5in'>283 K
     gates, 1 cycle/operation, 25.5 Gbits/sec (pipelined)</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<h1>Approximate glue-logic to estimate buffer sizes/latency</h1>

<p class=MsoNormal>This is only for the purpose of characterizing the whole
path from flash to memory, not to describe how the logic will be implemented</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

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<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>The approximate steps are as follows</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l15 level1 lfo25;tab-stops:list .5in'>software
     programs the key (16 bytes)</li>
 <li class=MsoNormal style='mso-list:l15 level1 lfo25;tab-stops:list .5in'>software
     programs mode of operation (encrypt/decrypt/pass thru)</li>
 <li class=MsoNormal style='mso-list:l15 level1 lfo25;tab-stops:list .5in'>after
     chip is enabled data is clocked into the input buffer (16*0.1 usec + 16*17ns-96
     clocks)</li>
 <li class=MsoNormal style='mso-list:l15 level1 lfo25;tab-stops:list .5in'>input
     is read in for decryption (44 clocks)</li>
 <li class=MsoNormal style='mso-list:l15 level1 lfo25;tab-stops:list .5in'>output
     is clocked out of the output buffer (2*17 ns  2 clocks)</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>total about 140 clocks per 16 bytes. Which will about equal
7M Bytes/sec throughput.</p>

<p class=MsoNormal>(This has to be increased by having double buffering in the
flash interface).</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>128 bit alignment overhead</b>:</p>

<p class=MsoNormal>And dma access has to be inflated to start from a 128 bit
boundary. And include complete 128 bit blocks. Hardware has to do this address
rounding and write back the requested data. This adds to some overhead. Worst
case is 2 page misses = 2*10usec= 120 clocks</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>CBC overhead:<o:p></o:p></b></p>

<p class=MsoNormal>When CBC mode is in use, it requires another 128 bits to be
read in (prev block). This could be included in the previous additional read,
otherwise adds another 60 clocks.</p>

<p class=MsoNormal>Together worst case is 3/2 pages extra in the beginning and
1 page at the end.</p>

<p class=MsoNormal>(when read address is in first half of 512 bit page,
previous 512 bits have to be read, when it is in second half of 512 bit page,
no previous page has to be read)</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Random Number generation:<o:p></o:p></b></p>

<p class=MsoNormal>The chip has to generate a cryptographically secure random
number or symmetric key for the re-encryption. </p>

<p class=MsoNormal>Current proposal:</p>

<p class=MsoNormal>Have a good random number generator (hardware based) on the
server to embed a second re-encryption key in the license. The chip modifies
this key as follows: during writing to flash the writing times to write fixed
size blocks is saved and an MD5 hash over these numbers is calculated<span
style="mso-spacerun: yes">  </span>(after scaling to same range). The hash over
several numbers should make it return a string of uniformly distributed bits
converted from a normal (or whatever) distribution in the writing time jitter.
This hash is saved for next download. The next time, the server-generated key
is concatenated to the hash and hashed again. This becomes the new re-encryption
key.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Problem 2:<o:p></o:p></b></p>

<p class=MsoNormal><b>DRAM encryption/decryption</b>: <b>(discussion)<o:p></o:p></b></p>

<p class=MsoNormal>The main problems for encrypting and decrypting data to and
from DRAM:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l8 level1 lfo28;tab-stops:list .5in'>We
     need both encryption and decryption since the data is modified by CPU,
     graphics read-modify-write etc</li>
 <li class=MsoNormal style='mso-list:l8 level1 lfo28;tab-stops:list .5in'>The
     memory interface does not know code from data or which module the request
     emerges from</li>
 <li class=MsoNormal style='mso-list:l8 level1 lfo28;tab-stops:list .5in'>The
     decrypt/encrypt operation will interface with performance of memory access</li>
 <li class=MsoNormal style='mso-list:l8 level1 lfo28;tab-stops:list .5in'>The
     data is accessed randomly. CPU accesses are due to cache misses.</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>So we have two approaches (ignoring the approach of doing
nothing at all!)</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l11 level1 lfo31;tab-stops:list .5in'><i>(Currently
     considered not feasible).</i> Have a uniform solution for encrypting and
     decrypting in the RI and at the output of flash decryption. See AES
     hardware performance numbers above. Assuming the full solution (10 round
     128 bit AES) is impossible, a 6 round AES takes 350 Gbytes of chosen
     plaintext and about ½ year to crack on a desktop CPU. Of-course we would
     change keys each time, so this would be almost infeasible. If we increase
     to 7 rounds, it increases to billions of years using known techniques. (5
     rounds has an attack based on few KB of data possible with 1 trillion
     calculations, so it is not safe). So 6 rounds and above are interesting
     reduced round variants of<span style="mso-spacerun: yes">
     </span>Rijndael. (assuming this should cost about 3-4 clocks per round, it
     is considered infeasible).</li>
 <li class=MsoNormal style='mso-list:l11 level1 lfo31;tab-stops:list .5in'>Tag
     program code in the content, and use an unused bit in the word to write
     this information bit. Detect the tag in the RI and do decryption on this
     block (ECB). That way we would cover all the program code, which is only a
     fraction of all memory accesses, and we do not need encryption in the RI,
     only decryption, assuming program code is not self-modifying.</li>
 <li class=MsoNormal style='mso-list:l11 level1 lfo31;tab-stops:list .5in'>The
     alternative is to do the previous operation in the MI, but since the MI
     cannot see the extra bits, it needs to carry the information in another
     form, like an additional signal (bit) or use a lookup table. Is it
     possible to lookup a table of, say 6-7 entries to decide whether or not to
     decrypt?</li>
</ul>

<p class=MsoNormal style='margin-left:.5in'>Note: for future content, where
copy protection is really valuable, it could be possible to have the code as a
contiguous block, like in a video player code. Then this scheme would be used
to protect the player decoder, which would have embedded in it the DRM scheme
(decrypt and decode). Then the table to be looked up can be made much smaller
or even just one region.</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l16 level1 lfo34;tab-stops:list .5in'>The
     last option is to do some form of masking of data on the bus by doing an
     xor before writing to DDR and an xor in the RI to invert while reading.</li>
</ul>

<p class=MsoNormal style='margin-left:.5in'>Current proposal:<span
style="mso-spacerun: yes">  </span>precompute for each of say, 16 segments of
DDR, MD5 hash(content re-encryption key, page address, serial number). The
content re-encryption key is 128 bits. The address is of the granularity of MB,
and serial number goes from 1N for each hash calculation. Each hash
calculation produces 128 bits or 16 bytes. Two hash calculations thus produce
32 bytes.</p>

<p class=MsoNormal style='margin-left:.5in'>For each memory segment we save
these 32 byte quantities, and as data is read from DDR or written to DDR the
xor with these quantities is performed by looking up the masking function
corresponding to that memory segment.</p>

<p class=MsoNormal style='text-align:justify'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Problem 3: <o:p></o:p></b></p>

<p class=MsoNormal><b>DRAM authentication (discussion)<o:p></o:p></b></p>

<p class=MsoNormal>The main problem of authenticating DDR content is that there
is too much data to be signature-checked constantly and since data is
constantly modified it is difficult to check against known signatures. There
are two possible protections against illegal code executing from external
memory:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l13 level1 lfo37;tab-stops:list .5in'>Make
     sure legal code resides in DDR where it is meant to be</li>
 <li class=MsoNormal style='mso-list:l13 level1 lfo37;tab-stops:list .5in'>Reduce
     the space in DDR from where illegal code can potentially execute.</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal style='margin-left:.25in'>Lets assume the CPU clock can
support this extra computation!</p>

<p class=MsoNormal style='margin-left:.25in'>Analyzing this possibility
(protecting memory ranges):</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>Assume
     we can map out from flash content the locations of critical code segments</li>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>As
     this content is DMA-ed to DDR, the destination regions are stored in a
     table</li>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>Every
     time the secure timer interrupt happens these regions are randomly checked
     for signature validity</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>Characterize
     a games CPU access to memory by mapping out regions of DDR that CPU
     reads/writes into (excluding frame buffers, etc). This could dynamically
     change, so one way might be to do the reverse: DMA requests through secure
     kernel to help demarcate regions used by non-CPU blocks.</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>We
     need to track CPU accesses from MI to identify any access to illegal
     regions.</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l17 level1 lfo40;tab-stops:list .5in'>To
     achieve that, we could do one of these in MI:</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<ul style='margin-top:0in' type=disc>
 <ul style='margin-top:0in' type=circle>
  <li class=MsoNormal style='mso-list:l17 level2 lfo40;tab-stops:list 1.0in'>Push
      all memory accesses from CPU to a storage and in the next secure timer
      trap check if any access falls in illegal range </li>
  <li class=MsoNormal style='mso-list:l17 level2 lfo40;tab-stops:list 1.0in'>In
      hardware, check memory address against a table (of say a few values) to
      see if it falls in an illegal region, if so, set a flag which will be
      checked in next secure timer interrupt. </li>
 </ul>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal style='margin-left:.5in'>Neither of these add latency to the
request, since it is a parallel operation with the actual data fetch. However
the number of requests may flood before they can be checked in the next secure
interrupt.</p>

<p class=MsoNormal><span style='mso-tab-count:1'>            </span>Some rough
calculation:</p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>Rough bcopy bandwidth at output of CPU at about 125 MHz
is about 1.18 Gbits/s</p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>=148 Mbytes/sec = 4.6 million requests per second
assuming a request reads in 32 bytes</p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>= about 4.6K requests every millisecond. So the storage
has to hold approx 5K addresses and</p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>in the secure interrupt 5K have to be validated against
a table of<span style="mso-spacerun: yes">  </span>known regions<span
style="mso-spacerun: yes">  </span>(if the table has N entries, thats worst
case N*5K*2 checks for the two boundaries). The context switch time is mostly
swapping SRAM contents in and out, which takes about 1usec per Kbyte.</p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>This number may be pruned to do random storage and
checks, or store not absolute addresses but in 1K granularity (for example). So
if an access is in the same 1K region as a previous access it does not have to
be stored. </p>

<p class=MsoNormal style='margin-left:1.0in;text-indent:-.25in;mso-list:l10 level1 lfo46;
tab-stops:list 1.0in'><![if !supportLists]><span style='font-family:Symbol'>·<span
style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
</span></span><![endif]>MD5 checking in software requires about 12-13 clocks
per byte. If entire code is about 1 MByte, that would take about 15x10^6
clocks. So if it has to be signature checked every one second, it would consume
about a tenth of a 200MHz CPU (if the CPU runs at 200MHz) and transfer about
1MB more from DDR to chip every second.</p>

<p class=MsoNormal>Note: all of these is feasible if the CPU can be made to run
faster. The extra cycles used to do the hash calculation and switching to
secure mode.</p>

<p class=MsoNormal><b>Appendices:<o:p></o:p></b></p>

<p class=MsoNormal><b>Criteria for AES core selection<o:p></o:p></b></p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Whether
     a vendor has synthesized and used the core in 0.18u and 0.13u technology</li>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Cost</li>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Input
     and output widths, whether fixed or programmable</li>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Has
     support for CBC or need to do in glue logic</li>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Throughput
     with and without pipelining</li>
 <li class=MsoNormal style='mso-list:l2 level1 lfo49;tab-stops:list .5in'>Size
     of core (gates)</li>
</ul>

<p class=MsoNormal style='margin-left:.25in'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Inventory of security software required in BB:<o:p></o:p></b></p>

<p class=MsoNormal>(Prior to run time software involving key generation will be
listed in manufacturing document)</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l7 level1 lfo52;tab-stops:list .5in'>AES
     encryption CBC mode</li>
 <li class=MsoNormal style='mso-list:l7 level1 lfo52;tab-stops:list .5in'>MD5
     signature checking </li>
 <li class=MsoNormal style='mso-list:l7 level1 lfo52;tab-stops:list .5in'>Random
     number generation software/driver for hardware</li>
 <li class=MsoNormal style='mso-list:l7 level1 lfo52;tab-stops:list .5in'>Public
     key software</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></b></p>

<p class=MsoNormal><b>Secure mode trap context switch operation:<o:p></o:p></b></p>

<p class=MsoNormal>To decide the overhead in context switching to determine
what is a reasonable interval for timer interrupts to secure mode.</p>

<p class=MsoNormal>(refer document BB secure mode operation for details)</p>

<p class=MsoNormal>Entering secure mode:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l12 level1 lfo55;tab-stops:list .5in'>Execute
     uncached load from secure timer</li>
 <li class=MsoNormal style='mso-list:l12 level1 lfo55;tab-stops:list .5in'>Swap
     internal SRAM to main memory using PI dma to create space for executing
     secure mode operation</li>
 <li class=MsoNormal style='mso-list:l12 level1 lfo55;tab-stops:list .5in'>Time
     for swapping is about 1usec for 1Kbyte, for entire 32Kbyte SRAM about 32
     usec.</li>
</ul>

<p class=MsoNormal>Exiting secure mode:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l9 level1 lfo58;tab-stops:list .5in'>Restore
     SRAM (same time for swapping)</li>
 <li class=MsoNormal style='mso-list:l9 level1 lfo58;tab-stops:list .5in'>flush
     Icache and Dcache</li>
 <li class=MsoNormal style='mso-list:l9 level1 lfo58;tab-stops:list .5in'>Store
     to secure mode register to turn off internal flash access</li>
 <li class=MsoNormal style='mso-list:l9 level1 lfo58;tab-stops:list .5in'>Return
     to application</li>
</ul>

<p class=MsoNormal><b><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></b></p>

<p class=MsoNormal><b>AES algorithm issues:<o:p></o:p></b></p>

<p class=MsoNormal>Assuming we will do encryption in software and decryption in
hardware. Just some points to note</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l0 level1 lfo61;tab-stops:list .5in'>The
     Sboxes (256 bytes) for decryption and encryption are different.</li>
 <li class=MsoNormal style='mso-list:l0 level1 lfo61;tab-stops:list .5in'>The
     results of key expansion 11*16 bytes =176 bytes have to be saved as state.</li>
 <li class=MsoNormal style='mso-list:l0 level1 lfo61;tab-stops:list .5in'>The
     key expansion computation involves 44*(S-box substitution, rotate, xor),
     the factor in brackets is done on 32 bit words.</li>
 <li class=MsoNormal style='mso-list:l0 level1 lfo61;tab-stops:list .5in'>There
     is less reason to consider doing that in hardware for computation reasons,
     but the space to implement key expansion alone is almost same as if the
     whole operation was implemented, in software. The logic is similar, but
     data is different.</li>
</ul>

<p class=MsoNormal><b><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></b></p>

<p class=MsoNormal><b>AES modes:<span style="mso-spacerun: yes">  </span><o:p></o:p></b></p>

<p class=MsoNormal>While encrypting data into flash, it maybe wise to use CBC
mode to randomize the encrypted text. On the other hand, it means reading in
one previous block of cipher-text extra before start of desired block. The
initialization vector could be a random number or timestamp, and need not be
secret. Or optionally we could only use CBC for the boot code data and ECB for
the rest of content. Since the boot code may have predictable code.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<h1>AES core resources:</h1>

<p class=MsoNormal>Tality</p>

<p class=MsoNormal><a href="http://www.tality.com/ip/aes/aes-flyer.html">http://www.tality.com/ip/aes/aes-flyer.html</a></p>

<p class=MsoNormal>Helion Technology</p>

<p class=MsoNormal><a href="http://www.heliontech.com/core2.htm">http://www.heliontech.com/core2.htm</a></p>

<p class=MsoNormal>Amphion</p>

<p class=MsoNormal><a href="http://www.amphion.com/cs5210.html">http://www.amphion.com/cs5210.html</a></p>

<p class=MsoNormal>Ocean Logic</p>

<p class=MsoNormal><a href="http://www.ocean-logic.com/pub/OL_AES.pdf">http://www.ocean-logic.com/pub/OL_AES.pdf</a></p>

<p class=MsoNormal>Secucore</p>

<p class=MsoNormal><a href="http://www.secucore.com/products.htm">http://www.secucore.com/products.htm</a></p>

<p class=MsoNormal>Cast Inc</p>

<p class=MsoNormal><a href="http://www.cast-inc.com/cores/aes/aes.pdf">http://www.cast-inc.com/cores/aes/aes.pdf</a></p>

<p class=MsoNormal>North Pole Engineering</p>

<p class=MsoNormal><a href="http://209.134.155.72/aescore.htm">http://209.134.155.72/aescore.htm</a></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>FPGA: </p>

<p class=MsoNormal><a
href="http://www.altera.com/literature/wp/wp_hcores_rijnfast.pdf">http://www.altera.com/literature/wp/wp_hcores_rijnfast.pdf</a></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>Dcrypt</p>

<p class=MsoNormal><a href="http://www.d-crypt.com/">http://www.d-crypt.com</a></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>Cryptographic Standards and Validation Program lists:</p>

<p class=MsoNormal><a href="http://csrc.nist.gov/cryptval/">http://csrc.nist.gov/cryptval/</a></p>

<p class=MsoNormal>(look at vendor lists, FIPS140-1 and 140-2 lists)</p>

<p class=MsoNormal><a href="http://csrc.nist.gov/cryptval/140-1/1401val.htm">http://csrc.nist.gov/cryptval/140-1/1401val.htm</a></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><b>Public key choices:<o:p></o:p></b></p>

<p class=MsoNormal>The public key cryptographic choices are standard RSA-like
PKI or the same equivalent using elliptic curves. The purpose for elliptic
curves is because certificates are order of 10 smaller and some operations are
faster.</p>

<p class=MsoNormal>The operations are:</p>

<ul style='margin-top:0in' type=disc>
 <li class=MsoNormal style='mso-list:l14 level1 lfo64;tab-stops:list .5in'>Signature
     verification of server on license</li>
 <li class=MsoNormal style='mso-list:l14 level1 lfo64;tab-stops:list .5in'>Decryption
     of license using private key</li>
 <li class=MsoNormal style='mso-list:l14 level1 lfo64;tab-stops:list .5in'>HR
     Depot certificate verification?</li>
</ul>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal>These are all not performance critical operations, hence
purely software decisions.</p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>

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