*******************************************************
11/21/02:  the RTL tree is tagged just prior to massive
checkin of verilog gated clock removal (bcp/* and src/*).

 cvs tag RTL_1_BASE bcp src include lib Makefile vsim

*******************************************************
11/12/02:  the RTL tree is tagged just prior to massive
checkin of verilog instance replacement (via jlib):

 cvs tag RTL_0_BASE bcp src include Makefile

(the lib tree was not tagged)

*******************************************************
in case you have a need to revert your workarea
to the state just prior to the instance replacment
checkin (circa 18:10 o-clock tonite) you can achieve by:

 cd to desired directory (e.g. bcp)
 cvs update -r RTL_0_BASE

*******************************************************
this will repopulate your workarea with the tree
existing BEFORE the aforementioned instance replacment.
(note:  if design has instantiated elements j_* then
 it has been affected by the instance replacement).

(see cvs man and rf/doc/infrastructure/SourceBranches.html
 for more info)