/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: arb.v,v 1.8 2003/01/24 23:07:36 berndt Exp $

module arb(clock, reset_l,
   dma_ready,
   sp_dma_request, sp_read_request,
   mem_read_request,
   mi_dma_request, mi_write_request, mi_read_request,
   cmd_dma_request, cmd_read_request,
   ri_read_request,
   pi_dma_request, pi_read_request,
   si_dma_request, si_read_request,
   ai_dma_request, ai_read_request,
   vi_dma_request, vi_read_request,
   ui_dma_request, ui_read_request,
   span_dma_request, span_read_request,
   sp_cbus_read_enable, sp_cbus_write_enable, sp_dma_grant, sp_read_grant,
   mem_cbus_write_enable,
   mi_cbus_read_enable, mi_cbus_write_enable, mi_cbus_grant,
   cmd_cbus_read_enable, cmd_cbus_write_enable, cmd_dma_grant, cmd_read_grant,
   ri_cbus_read_enable, ri_cbus_write_enable, ri_read_grant,
   pi_cbus_read_enable, pi_cbus_write_enable, pi_dma_grant, pi_read_grant,
   si_cbus_read_enable, si_cbus_write_enable, si_dma_grant, si_read_grant,
   ai_cbus_read_enable, ai_cbus_write_enable, ai_dma_grant, ai_read_grant,
   vi_cbus_read_enable, vi_cbus_write_enable, vi_dma_grant, vi_read_grant,
   ui_cbus_read_enable, ui_cbus_write_enable, ui_dma_grant, ui_read_grant,
   span_cbus_read_enable, span_cbus_write_enable, span_dma_grant,
   span_read_grant,
   cbus_select, cbus_command,
   rsp_cbus_dout, rsp_dbus_dout,
   rdp_cbus_dout, rdp_dbus_dout, rdp_ebus_dout,
   mi_cbus_dout,  mi_dbus_dout,
   pi_cbus_dout,  pi_dbus_dout,
   si_cbus_dout,  si_dbus_dout,
   vi_cbus_dout, 
   ai_cbus_dout, 
   ri_cbus_dout,  ri_dbus_dout,  ri_ebus_dout,
   ui_cbus_dout,  ui_dbus_dout,
   cbus_din, dbus_din, ebus_din
	);

`include "rcp.vh"

input clock;
input reset_l;

input dma_ready;
input sp_dma_request;
input sp_read_request;
input mem_read_request;
input mi_dma_request;
input mi_write_request;
input mi_read_request;
input cmd_dma_request;
input cmd_read_request;
input ri_read_request;
input pi_dma_request;
input pi_read_request;
input si_dma_request;
input si_read_request;
input ai_dma_request;
input ai_read_request;
input vi_dma_request;
input vi_read_request;
input ui_dma_request;
input ui_read_request;
input span_dma_request;
input span_read_request;

output sp_cbus_read_enable;
output sp_cbus_write_enable;
output sp_dma_grant;
output sp_read_grant;
output mem_cbus_write_enable;
output mi_cbus_read_enable;
output mi_cbus_write_enable;
output mi_cbus_grant;
output cmd_cbus_read_enable;
output cmd_cbus_write_enable;
output cmd_dma_grant;
output cmd_read_grant;
output ri_cbus_read_enable;
output ri_cbus_write_enable;
output ri_read_grant;
output pi_cbus_read_enable;
output pi_cbus_write_enable;
output pi_dma_grant;
output pi_read_grant;
output si_cbus_read_enable;
output si_cbus_write_enable;
output si_dma_grant;
output si_read_grant;
output ai_cbus_read_enable;
output ai_cbus_write_enable;
output ai_dma_grant;
output ai_read_grant;
output vi_cbus_read_enable;
output vi_cbus_write_enable;
output vi_dma_grant;
output vi_read_grant;
output ui_cbus_read_enable;
output ui_cbus_write_enable;
output ui_dma_grant;
output ui_read_grant;
output span_cbus_read_enable;
output span_cbus_write_enable;
output span_dma_grant;
output span_read_grant;
output [1:0] cbus_select;
output [2:0] cbus_command;

input	[31:0]	rsp_cbus_dout;
input	[63:0]	rsp_dbus_dout;
input	[31:0]	rdp_cbus_dout;
input	[63:0]	rdp_dbus_dout;
input	[7:0]	rdp_ebus_dout;
input	[31:0]	mi_cbus_dout;
input	[63:0]	mi_dbus_dout;
input	[31:0]	pi_cbus_dout;
input	[63:0]	pi_dbus_dout;
input	[31:0]	si_cbus_dout;
input	[63:0]	si_dbus_dout;
input	[31:0]	vi_cbus_dout;
input	[31:0]	ai_cbus_dout;
input	[31:0]	ri_cbus_dout;
input	[63:0]	ri_dbus_dout;
input	[7:0]	ri_ebus_dout;
input	[31:0]	ui_cbus_dout;
input	[63:0]	ui_dbus_dout;
output	[31:0]	cbus_din;
output	[63:0]	dbus_din;
output	[7:0]	ebus_din;

// 3-state C,D and E Bus removal logic

wire	[31:0]	cbus_din = rsp_cbus_dout | rdp_cbus_dout | mi_cbus_dout
			 | pi_cbus_dout  | si_cbus_dout  | vi_cbus_dout
			 | ai_cbus_dout  | ri_cbus_dout  | ui_cbus_dout;

wire	[63:0]	dbus_din = rsp_dbus_dout | rdp_dbus_dout | mi_dbus_dout
			 | pi_dbus_dout  | si_dbus_dout  
					 | ri_dbus_dout  | ui_dbus_dout;

wire	[7:0]	ebus_din = rdp_ebus_dout | ri_ebus_dout;

// output registers
reg sp_dma_grant;
reg sp_read_grant;
reg mi_cbus_grant;
reg cmd_dma_grant;
reg cmd_read_grant;
reg ri_read_grant;
reg pi_dma_grant;
reg pi_read_grant;
reg si_dma_grant;
reg si_read_grant;
reg ai_dma_grant;
reg ai_read_grant;
reg vi_dma_grant;
reg vi_read_grant;
reg ui_dma_grant;
reg ui_read_grant;
reg span_dma_grant;
reg span_read_grant;
reg [1:0] cbus_select;
reg [2:0] cbus_command;

// output pseudo register
reg sp_cbus_write_enable;
reg mem_cbus_write_enable;
reg mi_cbus_write_enable;
reg cmd_cbus_write_enable;
reg ri_cbus_write_enable;
reg pi_cbus_write_enable;
reg si_cbus_write_enable;
reg ai_cbus_write_enable;
reg vi_cbus_write_enable;
reg ui_cbus_write_enable;
reg span_cbus_write_enable;
reg sp_cbus_read_enable;
reg mi_cbus_read_enable;
reg cmd_cbus_read_enable;
reg ri_cbus_read_enable;
reg pi_cbus_read_enable;
reg si_cbus_read_enable;
reg ai_cbus_read_enable;
reg vi_cbus_read_enable;
reg ui_cbus_read_enable;
reg span_cbus_read_enable;

// internal registers
reg sp_dma_grant_a1;
reg sp_read_grant_a1;
reg mi_cbus_grant_a1;
reg cmd_dma_grant_a1;
reg cmd_read_grant_a1;
reg ri_read_grant_a1;
reg pi_dma_grant_a1;
reg pi_read_grant_a1;
reg si_dma_grant_a1;
reg si_read_grant_a1;
reg ai_dma_grant_a1;
reg ai_read_grant_a1;
reg vi_dma_grant_a1;
reg vi_read_grant_a1;
reg ui_dma_grant_a1;
reg ui_read_grant_a1;
reg span_dma_grant_a1;
reg span_read_grant_a1;
reg [DMA_DEVICE_SIZE-1:0] cbus_enable;
reg read_disable;

// state machine register
reg [2:0] state;
parameter
   STATE_IDLE 					= 0,
   STATE_DMA 					= 1,
   STATE_WRITE 				= 2,
   STATE_READ	 				= 3,
   STATE_RESPONSE				= 4,
   STATE_DELAY 				= 6;

// cbus enable decoder
// all states must decode to exactly one active enable
always @(cbus_enable or read_disable) begin
//compass statemachine adj state
	sp_cbus_write_enable = LOW;
	mem_cbus_write_enable = LOW;
	mi_cbus_write_enable = LOW;
	cmd_cbus_write_enable = LOW;
	ri_cbus_write_enable = LOW;
	pi_cbus_write_enable = LOW;
	si_cbus_write_enable = LOW;
	ai_cbus_write_enable = LOW;
	vi_cbus_write_enable = LOW;
	ui_cbus_write_enable = LOW;
	span_cbus_write_enable = LOW;

	if (read_disable) begin
		sp_cbus_read_enable = LOW;
		mi_cbus_read_enable = LOW;
		cmd_cbus_read_enable = LOW;
		ri_cbus_read_enable = LOW;
		pi_cbus_read_enable = LOW;
		si_cbus_read_enable = LOW;
		ai_cbus_read_enable = LOW;
		vi_cbus_read_enable = LOW;
		ui_cbus_read_enable = LOW;
		span_cbus_read_enable = LOW;
		end
	else begin
		sp_cbus_read_enable = HIGH;
		mi_cbus_read_enable = HIGH;
		cmd_cbus_read_enable = HIGH;
		ri_cbus_read_enable = HIGH;
		pi_cbus_read_enable = HIGH;
		si_cbus_read_enable = HIGH;
		ai_cbus_read_enable = HIGH;
		vi_cbus_read_enable = HIGH;
		ui_cbus_read_enable = HIGH;
		span_cbus_read_enable = HIGH;
		end

	// enable the selected write device
	case (cbus_enable)
		`CBUS_DEV_SP: begin
			sp_cbus_write_enable = HIGH;
			sp_cbus_read_enable = LOW;
			end
		`CBUS_DEV_MEM : begin
			mem_cbus_write_enable = HIGH;
			end
		`CBUS_DEV_MI : begin
			mi_cbus_write_enable = HIGH;
			mi_cbus_read_enable = LOW;
			end
		`CBUS_DEV_CMD : begin
			cmd_cbus_write_enable = HIGH;
			cmd_cbus_read_enable = LOW;
			end
		`CBUS_DEV_RI : begin
			ri_cbus_write_enable = HIGH;
			ri_cbus_read_enable = LOW;
			end
		`CBUS_DEV_PI : begin
			pi_cbus_write_enable = HIGH;
			pi_cbus_read_enable = LOW;
			end
		`CBUS_DEV_SI : begin
			si_cbus_write_enable = HIGH;
			si_cbus_read_enable = LOW;
			end
		`CBUS_DEV_AI : begin
			ai_cbus_write_enable = HIGH;
			ai_cbus_read_enable = LOW;
			end
		`CBUS_DEV_VI : begin
			vi_cbus_write_enable = HIGH;
			vi_cbus_read_enable = LOW;
			end
		`CBUS_DEV_UI : begin
			ui_cbus_write_enable = HIGH;
			ui_cbus_read_enable = LOW;
			end
		`CBUS_DEV_SPAN : begin
			span_cbus_write_enable = HIGH;
			span_cbus_read_enable = LOW;
			end
		default : begin
			sp_cbus_write_enable = HIGH;
			sp_cbus_read_enable = LOW;
			end
		endcase
	end


always @(posedge clock) begin
	sp_dma_grant <= sp_dma_grant_a1;
	sp_read_grant <= sp_read_grant_a1;
	mi_cbus_grant <= mi_cbus_grant_a1;
	cmd_dma_grant <= cmd_dma_grant_a1;
	cmd_read_grant <= cmd_read_grant_a1;
	span_dma_grant <= span_dma_grant_a1;
	span_read_grant <= span_read_grant_a1;
	ri_read_grant <= ri_read_grant_a1;
	pi_dma_grant <= pi_dma_grant_a1;
	pi_read_grant <= pi_read_grant_a1;
	si_dma_grant <= si_dma_grant_a1;
	si_read_grant <= si_read_grant_a1;
	ai_dma_grant <= ai_dma_grant_a1;
	ai_read_grant <= ai_read_grant_a1;
	vi_dma_grant <= vi_dma_grant_a1;
	vi_read_grant <= vi_read_grant_a1;
	ui_dma_grant <= ui_dma_grant_a1;
	ui_read_grant <= ui_read_grant_a1;
	end


always @(posedge clock) begin
	if (reset_l == 1'b0) begin
		sp_dma_grant_a1 <= LOW;
		sp_read_grant_a1 <= LOW;
		mi_cbus_grant_a1 <= LOW;
		cmd_dma_grant_a1 <= LOW;
		cmd_read_grant_a1 <= LOW;
		ri_read_grant_a1 <= LOW;
		pi_dma_grant_a1 <= LOW;
		pi_read_grant_a1 <= LOW;
		si_dma_grant_a1 <= LOW;
		si_read_grant_a1 <= LOW;
		ai_dma_grant_a1 <= LOW;
		ai_read_grant_a1 <= LOW;
		vi_dma_grant_a1 <= LOW;
		vi_read_grant_a1 <= LOW;
		ui_dma_grant_a1 <= LOW;
		ui_read_grant_a1 <= LOW;
		span_dma_grant_a1 <= LOW;
		span_read_grant_a1 <= LOW;

		cbus_enable <= 0;
		read_disable <= LOW;
		cbus_command <= `CBUS_CMD_IDLE;
		state <= STATE_IDLE;

		end
	else begin : main_block
		reg next_sp_dma_grant_a1;
		reg next_sp_read_grant_a1;
		reg next_mi_cbus_grant_a1;
		reg next_cmd_dma_grant_a1;
		reg next_cmd_read_grant_a1;
		reg next_ri_read_grant_a1;
		reg next_pi_dma_grant_a1;
		reg next_pi_read_grant_a1;
		reg next_si_dma_grant_a1;
		reg next_si_read_grant_a1;
		reg next_ai_dma_grant_a1;
		reg next_ai_read_grant_a1;
		reg next_vi_dma_grant_a1;
		reg next_vi_read_grant_a1;
		reg next_ui_dma_grant_a1;
		reg next_ui_read_grant_a1;
		reg next_span_dma_grant_a1;
		reg next_span_read_grant_a1;
		reg next_read_disable;
		reg [1:0] next_cbus_select;
		reg [2:0] next_cbus_command;
		
		next_sp_dma_grant_a1 = LOW;
		next_sp_read_grant_a1 = LOW;
		next_mi_cbus_grant_a1 = LOW;
		next_cmd_dma_grant_a1 = LOW;
		next_cmd_read_grant_a1 = LOW;
		next_ri_read_grant_a1 = LOW;
		next_pi_dma_grant_a1 = LOW;
		next_pi_read_grant_a1 = LOW;
		next_si_dma_grant_a1 = LOW;
		next_si_read_grant_a1 = LOW;
		next_ai_dma_grant_a1 = LOW;
		next_ai_read_grant_a1 = LOW;
		next_vi_dma_grant_a1 = LOW;
		next_vi_read_grant_a1 = LOW;
		next_ui_dma_grant_a1 = LOW;
		next_ui_read_grant_a1 = LOW;
		next_span_dma_grant_a1 = LOW;
		next_span_read_grant_a1 = LOW;
		next_read_disable = LOW;
		next_cbus_select = 'bx;
		next_cbus_command = `CBUS_CMD_IDLE;

		// arbitrate the cbus
		case (state)
			STATE_IDLE : begin
				if (sp_read_request && !sp_read_grant) begin
					// sp response data
					next_sp_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_SP;
					state <= STATE_RESPONSE;
					end
				else if (mem_read_request && !sp_read_grant) begin
					// sp response data
					next_sp_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_MEM;
					state <= STATE_RESPONSE;
					end
				else if (pi_read_request && !pi_read_grant) begin
					// pi response data
					next_pi_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_PI;
					state <= STATE_RESPONSE;
					end
				else if (si_read_request && !si_read_grant) begin
					// si response data
					next_si_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_SI;
					state <= STATE_RESPONSE;
					end
				else if (ai_read_request && !ai_read_grant) begin
					// ai response data
					next_ai_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_AI;
					state <= STATE_RESPONSE;
					end
				else if (vi_read_request && !vi_read_grant) begin
					// vi response data
					next_vi_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_VI;
					state <= STATE_RESPONSE;
					end
				else if (ui_read_request && !ui_read_grant) begin
					// ui response data
					next_ui_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_UI;
					state <= STATE_RESPONSE;
					end
				else if (ri_read_request && !ri_read_grant) begin
					// ri response data
					next_ri_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_RI;
					state <= STATE_RESPONSE;
					end
				else if (span_read_request && !span_read_grant) begin
					// dp span response data
					next_span_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_SPAN;
					state <= STATE_RESPONSE;
					end
				else if (cmd_read_request && !cmd_read_grant) begin
					// dp command response data
					next_cmd_read_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_DATA;
					cbus_enable <= `CBUS_DEV_CMD;
					state <= STATE_RESPONSE;
					end
				else if (vi_dma_request && dma_ready) begin
					// vi dma request
					next_vi_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_VI;
					state <= STATE_DMA;
					end
				else if (ui_dma_request && dma_ready) begin
					// ui dma request
					next_ui_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_UI;
					state <= STATE_DMA;
					end
				else if (ai_dma_request && dma_ready) begin
					// ai dma request
					next_ai_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_AI;
					state <= STATE_DMA;
					end
				else if (si_dma_request && dma_ready) begin
					// si dma request
					next_si_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_SI;
					state <= STATE_DMA;
					end
				else if (pi_dma_request && dma_ready) begin
					// pi dma request
					next_pi_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_PI;
					state <= STATE_DMA;
					end
				else if (mi_dma_request && dma_ready) begin
					// mi dma request
					next_mi_cbus_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_MI;
					state <= STATE_DMA;
					end
				else if (sp_dma_request && dma_ready) begin
					// sp dma request
					next_sp_dma_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_SP;
					state <= STATE_DMA;
					end
				else if (cmd_dma_request && dma_ready) begin
					// dp command dma request
					next_cmd_dma_grant_a1 = HIGH;
					cbus_enable <= `CBUS_DEV_CMD;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					state <= STATE_DMA;
					end
				else if (span_dma_request && dma_ready) begin
					// dp span dma request
					next_span_dma_grant_a1 = HIGH;
					cbus_enable <= `CBUS_DEV_SPAN;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					state <= STATE_DMA;
					end
				else if (mi_write_request && !mi_cbus_grant) begin
					// mi write request
					next_mi_cbus_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_MI;
					state <= STATE_WRITE;
					end
				else if (mi_read_request && !mi_cbus_grant) begin
					// mi read request
					next_mi_cbus_grant_a1 = HIGH;
					next_read_disable = HIGH;
					next_cbus_select = `CBUS_SEL_ADDR;
					cbus_enable <= `CBUS_DEV_MI;
					state <= STATE_READ;
					end
				else begin
					state <= STATE_IDLE;
					end
				end

			STATE_DMA : begin
				next_cbus_select = `CBUS_SEL_LEN;
				next_cbus_command = `CBUS_CMD_DMA;
				state <= STATE_DELAY;
				end

			STATE_WRITE : begin
				next_cbus_select = `CBUS_SEL_DATA;
				next_cbus_command = `CBUS_CMD_WRITE;
				state <= STATE_DELAY;
				end

			STATE_READ : begin
				next_cbus_command = `CBUS_CMD_READ;
				state <= STATE_DELAY;
				end

			STATE_RESPONSE : begin
				next_cbus_command = `CBUS_CMD_RSP;
				state <= STATE_DELAY;
				end

			STATE_DELAY : begin
				state <= STATE_IDLE;
				end

			default : begin
				state <= STATE_IDLE;
				end
			endcase

		sp_dma_grant_a1 <= next_sp_dma_grant_a1;
		sp_read_grant_a1 <= next_sp_read_grant_a1;
		mi_cbus_grant_a1 <= next_mi_cbus_grant_a1;
		cmd_dma_grant_a1 <= next_cmd_dma_grant_a1;
		cmd_read_grant_a1 <= next_cmd_read_grant_a1;
		span_dma_grant_a1 <= next_span_dma_grant_a1;
		span_read_grant_a1 <= next_span_read_grant_a1;
		ri_read_grant_a1 <= next_ri_read_grant_a1;
		pi_dma_grant_a1 <= next_pi_dma_grant_a1;
		pi_read_grant_a1 <= next_pi_read_grant_a1;
		si_dma_grant_a1 <= next_si_dma_grant_a1;
		si_read_grant_a1 <= next_si_read_grant_a1;
		ai_dma_grant_a1 <= next_ai_dma_grant_a1;
		ai_read_grant_a1 <= next_ai_read_grant_a1;
		vi_dma_grant_a1 <= next_vi_dma_grant_a1;
		vi_read_grant_a1 <= next_vi_read_grant_a1;
		ui_dma_grant_a1 <= next_ui_dma_grant_a1;
		ui_read_grant_a1 <= next_ui_read_grant_a1;

		read_disable <= next_read_disable;
		cbus_command <= next_cbus_command;
		cbus_select <= next_cbus_select;
		end
	end
endmodule