/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: at_ms.v,v 1.4 2003/01/15 03:34:09 berndt Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      at_ms
// description:	Attribute buffers for memspan unit. Unlike the other
//		attribute buffers, this is a true fifo of data sampled
//		during ew_ep_startspan, when the end address is on
//		the ew_addr bus. The start address and count are piped
//		one stage to line up with end. The other inputs are
//		piped 4 stages in the edge walker to avoid overwriting
//		the last span of the previous primitive, and are sampled
//		with the other bits. The spanbufrd input pops the fifo.
//		The spanbufmt output is true if either the fifo is
//		truely empty, or of a span address overlap is detected,
//		in which case a delay is inserted before letting the
//		memspan have the span request packet, to allow time for
//		the offending span to be physically written to memory
//		before the colliding span is read into the spanbuf.
//
// designer:    Phil Gossett
// date:        6/11/95
//
////////////////////////////////////////////////////////////////////////

module at_ms (clk, start_gclk, reset_l, ew_ep_startspan,
	ew_addr, ew_length, ew_load, ew_load_tlut, ew_left, spanbufrd,
	ms_xi, ms_xf, ms_count, ms_load, ms_load_tlut, ms_xdec, spanbufmt);

input clk;
input start_gclk;
input reset_l;
input ew_ep_startspan;
input [19:0] ew_addr;
input [11:0] ew_length;
input ew_load;
input ew_load_tlut;
input ew_left;
input spanbufrd;

output [19:0] ms_xi;		// from ew (fifo)
output [11:0] ms_xf;		// from ew (fifo)
output [11:0] ms_count;		// from ew (fifo)
output ms_load;			// tile(34),block(33),tlut(30) (pipe, fifo)
output ms_load_tlut;		// tlut(30)                    (pipe, fifo)
output ms_xdec;			// primitives (36,24,25,0f-08) (pipe, fifo)
output spanbufmt;

reg [11:0] reg_count;
reg [19:0] reg_xi;

wire [63:0] d_lat;		// delayed latched input

wire [2:0] span_wrp;		// write pointer

wire span_a_g;
wire span_b_g;
wire span_c_g;
wire span_d_g;
wire span_e_g;

wire [55:0] span_a;		// latch outputs
wire [55:0] span_b;
wire [55:0] span_c;
wire [55:0] span_d;
wire [55:0] span_e;

wire [2:0] span_sel;		// read counter select

reg [2:0] span_wrp_1d;		// delays for spanbufmt
reg [2:0] span_wrp_2d;
reg [2:0] span_wrp_3d;
reg [2:0] span_wrp_4d;
reg [2:0] span_wrp_5d;

// delay start and count to line up with end and startspan
always @(posedge clk)
  if (start_gclk) begin
	reg_xi    <= ew_addr;
	reg_count <= ew_length;
end

// generate latch enable for fifo
at_ctw5 ctspang	(.clk(clk), .rst(reset_l), .enb(start_gclk & ew_ep_startspan), .z(span_wrp),
	.a(span_a_g), .b(span_b_g), .c(span_c_g), .d(span_d_g), .e(span_e_g));

// instanciated latches
assign d_lat = { 17'b0,~ew_left,ew_load,ew_load_tlut,reg_count,reg_xi,ew_addr[11:0] };
at_latch56 spana (.clk(clk), .g(span_a_g), .i(d_lat[55:0]), .z(span_a));
at_latch56 spanb (.clk(clk), .g(span_b_g), .i(d_lat[55:0]), .z(span_b));
at_latch56 spanc (.clk(clk), .g(span_c_g), .i(d_lat[55:0]), .z(span_c));
at_latch56 spand (.clk(clk), .g(span_d_g), .i(d_lat[55:0]), .z(span_d));
at_latch56 spane (.clk(clk), .g(span_e_g), .i(d_lat[55:0]), .z(span_e));

// generate read pointer for fifo
at_ctr5 ctspans	(.clk(clk), .rst(reset_l), .enb(spanbufrd), .z(span_sel));

// read latches with bit assignments and padding (unused latches eaten)
assign {ms_xdec,ms_load,ms_load_tlut,ms_count,ms_xi,ms_xf} =
	(span_sel[2] ?
		span_e[54:0] :
		(span_sel[1] ?
			(span_sel[0] ? span_d[54:0] : span_c[54:0]) :
			(span_sel[0] ? span_b[54:0] : span_a[54:0])));

// delay when ms sees fifo loaded by 5 cycles (pipe slip for LOD)
always @(posedge clk)
  if (start_gclk) begin
	span_wrp_1d <= span_wrp;
	span_wrp_2d <= span_wrp_1d;
	span_wrp_3d <= span_wrp_2d;
	span_wrp_4d <= span_wrp_3d;
	span_wrp_5d <= span_wrp_4d;
end

assign spanbufmt = (span_wrp_5d == span_sel);

endmodule // at_ms