dpmlt020m.vmd
1.79 KB
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/**************************************************************/
/* Verilog module of datapath cell dpmlt020m */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Chunling Liu Compass June 11, 92 */
/* */
/* The following is the port description */
/* Data ports */
/* X : the input port */
/* Y : the input port */
/* MSB : the output port */
/* LSB : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* Y_Bus_Size : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/**************************************************************/
module dpmlt020m(X, Y, MSB, LSB);
parameter WORDSIZE = 8, Y_Bus_Size = 7, DELAY = 30, BF = 1;
input [WORDSIZE-1:0] X, Y;
output [WORDSIZE-1:0] MSB, LSB;
function [2*WORDSIZE-1:0] mlt;
input [WORDSIZE-1:0] x;
input [WORDSIZE-1:0] y;
reg [WORDSIZE+Y_Bus_Size-1:0] z;
reg [Y_Bus_Size-1:0] y1;
integer i;
begin
y1 = y[Y_Bus_Size-1:0];
z = x * {{4'b0000},y1};
//
if (WORDSIZE > Y_Bus_Size)
begin
for (i = Y_Bus_Size; i < WORDSIZE; i = i+1)
mlt[i] = y[i];
mlt[Y_Bus_Size-1:0] = z[Y_Bus_Size-1:0];
end
else
mlt[WORDSIZE-1:0] = z[Y_Bus_Size-1:0];
mlt[2*WORDSIZE-1:WORDSIZE] = z[WORDSIZE+Y_Bus_Size-1:Y_Bus_Size];
end
endfunction
assign #DELAY {MSB, LSB} = mlt(X,Y);
endmodule