dpnor1021.vmd
1.43 KB
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/**************************************************************/
/* Verilog module of datapath cell DPNOR1021 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A1 : the input port */
/* INST : the control input port */
/* ZN : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpnor1021(A1, INST, ZN);
parameter WORDSIZE = 8, DELAY = 1, BF = 1;
input [WORDSIZE-1:0] A1;
input INST;
output [WORDSIZE-1:0] ZN;
function [WORDSIZE-1:0] n_or;
input [WORDSIZE-1:0] A1;
input INST;
integer i;
begin
i = 0;
for (i = 0; i < WORDSIZE; i = i+1)
n_or[i] = ~(A1[i] | INST);
end
endfunction
assign #DELAY ZN = n_or (A1, INST);
endmodule