// VERSION:1.00 DATE:2000/03/19 OpenCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module AAPLSIOH33 ( AVDD1, AGND1, DVDD1, DGND1, AVDD, AGND );
    input AVDD;
    input AGND;
    output AVDD1;
    output AGND1;
    output DVDD1;
    output DGND1;

    buf ( _AVDD, AVDD );
    buf ( _AGND, AGND );
    buf ( AVDD1, _AVDD );
    buf ( DVDD1, _AVDD );
    buf ( AGND1, _AGND );
    buf ( DGND1, _AGND );

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine