/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_bias
-- Date Created: Tue Jul 16 14:01:11 2002

*******************************************************************************/


`timescale 1 ns / 1 ps  // timescale for following modules

// -------------------------------------------------------------------
//  Copyright 2001 VAutomation Inc. Nashua NH USA. All rights reserved.
//  This software is provided under license and contains proprietary
//  and confidential material which is the property of VAutomation Inc.
//  HTTP://www.vautomation.com
// --------------------------------------------------------------------
//  File Name: $Workfile: vusb_bias.vhdl$
//  Revision: $Revision: 1.4 $
// 
//  Description:
//       This module should be instantiated at the same level as
//  host_ctl.  It is used to model the resistors on the usb dplus and
//  dminus signals.
// 
//  
// --------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// --------------------------------------------------------------------
//  Revision History
//  $Log: 
//   5    VUSB      1.4         4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   4    VUSB      1.3         11/7/01 9:00:56 AM     Tom Frechette   Bring in 
//         vbus sense to turn off dp_high and dm_high. Change the polarity of 
//         the dp_low and dm_low.
//   3    VUSB      1.2         6/28/01 9:27:58 AM     Tom Frechette   Added 
//         control to turn off drives when others are driving the lines.
//   2    VUSB      1.1         6/21/01 10:41:25 AM    Tom Frechette   Added 
//         comments.
//   1    VUSB      1.0         6/15/01 2:30:47 PM     Tom Frechette   
//  $
// --------------------------------------------------------------------
module vusb_bias (usb_dp_high,
   usb_dp_low_n,
   usb_dm_high,
   usb_dm_low_n,
   tb_is_device,
   dplus,
   dminus);
input   usb_dp_high; 
input   usb_dp_low_n; 
input   usb_dm_high; 
input   usb_dm_low_n; 
input   tb_is_device; 
inout   dplus; 
inout   dminus; 
wire    VHDL2V_dplus; 
wire    VHDL2V_dminus; 
wire    dplus; 
wire    dminus; 
reg     dplus_i; 
reg     dminus_i; 
reg     fight_dp; 
reg     fight_dm; 
reg     drive_dm; 
reg     drive_dp; 
//  drive out the signals after 1 nsec to avoid contention

bufif0 (highz1,weak0)
	g1(dplus, 1'b0, 1'b0) ,
	g2(dminus, 1'b0,1'b0) ;

initial 
   begin
   drive_dp = 1'b 1;	
   end

initial 
   begin
   drive_dm = 1'b 1;	
   end

initial 
   begin
   fight_dm = 1'b 0;	
   end

initial 
   begin
   fight_dp = 1'b 0;	
   end

initial 
   begin
   dminus_i = 1'b z;	
   end

initial 
   begin
   dplus_i = 1'b z;	
   end

assign #(1) dplus = ((drive_dp === 1'b 1) & (tb_is_device !== 1'b0) & (usb_dp_high !== 1'b1)) ? dplus_i : 
	1'b z; 
assign #(1) dminus = ((drive_dm === 1'b 1) & (usb_dm_low_n !== 1'b0))  ? dminus_i : 
	1'b z; 
//  determine whether someone else is driving the signals and yield to them

always @( dplus ) 
fight_dp = dplus === 1'b x ? 1'b 1 : 
	1'b 0; 

always @( dminus ) 
fight_dm = dminus === 1'b x ? 1'b 1 : 
	1'b 0; 
//  if no one is driving the signals then drive them

always @( drive_dp or fight_dp or dplus ) 
drive_dp = drive_dp === 1'b 1 & fight_dp === 1'b 0 | 
	dplus === 1'b Z ? 1'b 1 : 
	1'b 0; 

always @( drive_dm or fight_dm or dminus ) 
drive_dm = drive_dm === 1'b 1 & fight_dm === 1'b 0 | 
	dminus === 1'b Z ? 1'b 1 : 
	1'b 0; 

always @( tb_is_device ) 
dplus_i =  tb_is_device === 1'b 1 ? 1'b 1 : 
	1'b 0; 

always @( usb_dm_high ) 
dminus_i = usb_dm_high === 1'b 1 ? 1'b 1 : 
	1'b 0; 

endmodule // module vusb_bias