/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_bvci
-- Date Created: Tue Jul 16 13:59:40 2002

*******************************************************************************/


`timescale 1 ns / 1 ns // timescale for following modules

// ----------------------------------------------------------------------------
//  Copyright 2000 VAutomation Inc. Nashua NH USA. All rights reserved.
//  This software is provided under license and contains proprietary
//  and confidential material which is the property of VAutomation Inc.
//  HTTP://www.vautomation.com
// ----------------------------------------------------------------------------
//  File Name: $Workfile: vusb_bvci.vhdl$
//  Revision: $Revision: 1.3 $
//  Description:
// 
//  Description:
//               This is the top level file for the VUSB 1.1 core with a BVCI
//               interface. It instantiates the following blocks:
// 
//                     vusb_ratematch    - rate match logic
//                     vusb_sie          - serial interface logic
//                     vusb_dpllnrzi     - digital phase lock loop and non return 
//                                         to zero inverted logic
//                     vusb_fifo         - special fifo for usb 1.1
//                     vusb_up_int_bvci  - register file for usb 1.1 with bvci
//                                         interface.
// -----------------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// -----------Revision History--------------------------------------------------
//  $Log: 
//   35   VUSB      1.34        7/5/02 2:00:52 PM      Will Sanborn    Removed 
//         hub signals, which were not used.
//   34   VUSB      1.33        6/27/02 3:20:14 PM     Will Sanborn    Modified 
//         outputs in ratematch block, so OE signal goes active before the data 
//         signals on DPO and DMO.
//   33   VUSB      1.32        4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   32   VUSB      1.31        2/14/02 2:32:26 PM     Tom Frechette   Moved 
//         single ended transceiver logic to sie.
//   31   VUSB      1.30        2/12/02 10:15:44 AM    Tom Frechette   removing 
//         the flush from the status fifo.
//   30   VUSB      1.29        2/11/02 3:39:18 PM     Tom Frechette   making 
//         clocks and resets uniform.
//   29   VUSB      1.28        2/11/02 3:08:30 PM     Tom Frechette   Removing 
//         all fifo_reset signals.
//   28   VUSB      1.27        2/11/02 3:04:03 PM     Tom Frechette   Moving 
//         fifo flush into fifo module.
//   27   VUSB      1.26        2/11/02 2:53:15 PM     Tom Frechette   Fixing 
//         reset stuff.
//   26   VUSB      1.25        2/8/02 11:25:57 AM     Tom Frechette   Changed 
//         name of interrupt.
//   25   VUSB      1.24        2/7/02 4:48:37 PM      Tom Frechette   Added 
//         async resets and fixed names.
//   24   VUSB      1.23        12/10/01 1:57:56 PM    Tom Frechette   Fixed 
//         reset connection to dpll component.
//   23   VUSB      1.22        11/7/01 9:00:56 AM     Tom Frechette   Bring in 
//         vbus sense to turn off dp_high and dm_high. Change the polarity of 
//         the dp_low and dm_low.
//   22   VUSB      1.21        10/30/01 11:05:41 AM   Tom Frechette   Removed 
//         un-necessary logic to get rid synthesis warnings.
//   21   VUSB      1.20        10/10/01 9:28:58 AM    Tom Frechette   Changed 
//         stat fifo rst from clr to rst.
//   20   VUSB      1.19        10/4/01 10:33:49 AM    Tom Frechette   Added 
//         flush to up_int to clear out fifo state machines.
//   19   VUSB      1.18        8/7/01 9:25:05 AM      Monika Leary    Fixed 
//         jstate connection to up_int
//   18   VUSB      1.17        7/31/01 11:25:23 AM    Monika Leary    Added 
//         low_speed_en input to vusb_ratematch
//   17   VUSB      1.16        7/25/01 3:41:34 PM     Tom Frechette   Changed 
//         FIFO Parameter Names.
//   16   VUSB      1.15        7/23/01 4:08:34 PM     Tom Frechette   Added 
//         debug signals.
//   15   VUSB      1.14        7/23/01 2:42:29 PM     Tom Frechette   Added 
//         debug bus.
//   14   VUSB      1.13        7/23/01 2:25:04 PM     Tom Frechette   Added 
//         debug port.
//   13   VUSB      1.12        7/18/01 12:01:13 PM    Tom Frechette   Changed 
//         fifo sizes to 8.
//   12   VUSB      1.11        7/3/01 4:42:07 PM      Tom Frechette   Changed 
//         mode to a constant in vusb_cfg.
//   11   VUSB      1.10        6/22/01 9:30:27 AM     Tom Frechette   Changed 
//         name of sync reset constant
//   10   VUSB      1.9         6/22/01 9:10:00 AM     Tom Frechette   Changed 
//         name of config package
//   9    VUSB      1.8         6/21/01 10:41:50 AM    Tom Frechette   Changed 
//         user to work library
//   8    VUSB      1.7         6/21/01 9:27:29 AM     Tom Frechette   Changed 
//         names of components to add VUSB prefix.
//   7    VUSB      1.6         6/15/01 3:28:10 PM     Tom Frechette   Works 
//         with Arc
//   6    VUSB      1.5         6/12/01 4:17:31 PM     Tom Frechette   I don't 
//         know!
//         
//   5    VUSB      1.4         5/25/01 9:05:14 AM     Tom Frechette   Added 
//         fifo to this level
//   4    VUSB      1.3         5/21/01 2:12:14 PM     Tom Frechette   Added 
//         ratematch
//   3    VUSB      1.2         5/16/01 3:26:48 PM     Tom Frechette   Removed 
//         hc_mode en from top level. It wasn't connected to anything.
//   2    VUSB      1.1         5/10/01 8:24:21 AM     Tom Frechette   Changed 
//         address name and changed t_wdata bus widths to conform to BVCI
//   1    VUSB      1.0         5/2/01 4:03:43 PM      Tom Frechette   
//  $
//  $NoKeywords$
// -----------------------------------------------------------------------------
// ------------------------------------------------------------------------------
//  Copyright 1995 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and 
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_cfg.vhd	USB Configuration file.
// 
//  Revision: $Revision: 1.3 $
// 
//  Description: A Package file for the usb core that defines global usb constants
//      that contol how the VUSB core is synthesised.
// 
// ---------------------------------------------------------------------------
//  This product is licensed to:
//  $name$ of $company$
//  for use at site(s): 
//  $site$
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   32   VUSB      1.31        7/5/02 9:15:50 AM      Chris Kolb      Moved 
//         VUSB build configruation Revision constant to vusb_cfg, and updated 
//         the rev number to 3.0.
//   31   VUSB      1.30        4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   30   VUSB      1.29        3/18/02 10:52:11 AM    Tom Frechette   Changed 
//         IRQ_NUM default to 0x0.
//   29   VUSB      1.28        3/15/02 2:39:08 PM     Tom Frechette   Added 
//         Interupt info into add_info register.
//   28   VUSB      1.27        2/7/02 4:49:00 PM      Tom Frechette   Removed 
//         sync config variable.
//   27   VUSB      1.26        8/23/01 9:48:58 AM     Tom Frechette   
//   26   VUSB      1.25        7/25/01 3:41:35 PM     Tom Frechette   Changed 
//         FIFO Parameter Names.
//   25   VUSB      1.24        7/10/01 3:03:41 PM     Tom Frechette   Moved 
//         HOST comment for verilog.
//   24   VUSB      1.23        7/6/01 7:44:00 AM      Tom Frechette   Added 
//         host comments around host constant to make it look like vusb_sie.
//   23   VUSB      1.22        7/6/01 7:34:33 AM      Tom Frechette   Added 
//         device constant comment for ARC.
//   22   VUSB      1.21        7/3/01 4:42:08 PM      Tom Frechette   Changed 
//         mode to a constant in vusb_cfg.
//   21   VUSB      1.20        6/22/01 3:09:48 PM     Tom Frechette   Changed 
//         endpoint number.
//   20   VUSB      1.19        6/21/01 9:59:56 AM     Tom Frechette   Changed 
//         the name and added fifo constants
//   19   VUSB      1.18        6/21/01 9:51:24 AM     Tom Frechette   
//   18   VUSB      1.17        5/25/01 10:25:08 AM    Monika Leary    Set 
//         synchronous reset constant to '1'
//   17   VUSB      1.16        5/17/01 2:52:48 PM     Monika Leary    Added 
//         USE_SYNC_RESET constant
//   16   VUSB      1.15        12/14/00 8:42:11 AM    Christopher Meyers RCS 
//         Keyword To StarTeam Keyword Translation
//   15   VUSB      1.14        12/13/00 7:58:39 PM    Chris Kolb      Removed 
//         the HOST_WITHOUT_HUB constant. This control is now a Endpt0 control 
//         register bit in up_int.vhd.
//   14   VUSB      1.13        12/13/00 7:58:31 PM    Gregory Recupero Removed 
//         ^M's
//   13   VUSB      1.12        12/13/00 7:58:26 PM    Mark Pettigrew  
//         ulogicified source - no functional changes
//   12   VUSB      1.11        12/13/00 7:58:19 PM    Chris Kolb      Change 
//         type of HOST_WITHOUT_HUB from std_logic to integer so that it could 
//         be used to initialize a _synopsysTM(TM) compatible generic.
//   11   VUSB      1.10        12/13/00 7:58:14 PM    Chris Kolb      Set 
//         constant to support Host to Low Speed device thru a hub.
//   10   VUSB      1.9         12/13/00 7:58:07 PM    Chris Kolb      Changed 
//         LOW_SPEED_DEV constant to type integer to support generics.
//   9    VUSB      1.8         12/13/00 7:57:58 PM    Christopher Meyers 
//         removed ASIC_IMPLEMENTATION constant
//   8    VUSB      1.7         12/13/00 7:57:46 PM    Chris Kolb      Remove 
//         ^M's. No functional changes.
//   7    VUSB      1.6         12/13/00 7:57:39 PM    Chris Kolb      Added 
//         HOST_WITHOUT_HUB constant to support new code in the DPLLNRZI.
//   6    VUSB      1.5         12/13/00 7:57:19 PM    Chris Kolb      Turned 
//         host mode back on.
//   5    VUSB      1.4         12/13/00 7:57:12 PM    Chris Kolb      Reverted 
//         to device only implementation.
//   4    VUSB      1.3         12/13/00 7:57:08 PM    Chris Kolb      Added 
//         revision string.
//   3    VUSB      1.2         12/13/00 7:57:03 PM    Chris Kolb      Enabled 
//         implementation of embedded host functions.
//   2    VUSB      1.1         12/13/00 7:56:58 PM    Chris Kolb      Added 
//         IMPLEMENT_EMBEDED_HOST constant.
//   1    VUSB      1.0         12/13/00 7:56:51 PM    Chris Kolb      initial 
//         revision
//  $
// 
// 
// ------------------------------------------------------------------------------
module vusb_bvci (clk,
   rst,
   rst_a,
   usb_clk48,
   usb_rst48,
   usb_rst48_a,
   vusb_i_cmdack,
   vusb_i_rdata,
   vusb_i_reop,
   vusb_i_rspval,
   vusb_i_address,
   vusb_i_be,
   vusb_i_cmd,
   vusb_i_cmdval,
   vusb_i_eop,
   vusb_i_rspack,
   vusb_i_wdata,
   vusb_t_address,
   vusb_t_be,
   vusb_t_cmd,
   vusb_t_cmdval,
   vusb_t_eop,
   vusb_t_rspack,
   vusb_t_wdata,
   vusb_t_cmdack,
   vusb_t_rdata,
   vusb_t_reop,
   vusb_t_rspval,
   vusb_irq,
   usb_rcv,
   usb_dp,
   usb_dm,
   usb_vbus_in,
   usb_dpo,
   usb_dmo,
   usb_oe_n,
   usb_speed,
   usb_suspnd,
   usb_dp_high,
   usb_dp_low_n,
   usb_dm_high,
   usb_dm_low_n,
   usb_id,
   usb_a_vbus_vld,
   usb_sess_vld,
   usb_b_sess_end,
   usb_vbus_on,
   usb_vbus_chg,
   usb_vbus_dschg);
// ---------------------------ENTITY---------------------

 		// file containing translation of VHDL package 'vusb_cfg' 

parameter lsdev = 0;
`include "vusb_cfg.vh"
input   clk; //  system clock
input   rst; //  system  sync reset
input   rst_a; //  system async reset
input   usb_clk48; //  DPLL input clock
input   usb_rst48; //  48 mhz  sync reset
input   usb_rst48_a; //  48 mhz async reset
input   vusb_i_cmdack; //  init. command acknowledge
input   [31:0] vusb_i_rdata; //  init. read data
input   vusb_i_reop; //  init. response end of packet
input   vusb_i_rspval; //  init. response valid
output   [31:0] vusb_i_address; //  init. address
output   [3:0] vusb_i_be; //  init. byte enables
output   [1:0] vusb_i_cmd; //  init. command
output   vusb_i_cmdval; //  init. command valid
output   vusb_i_eop; //  init. end of packet
output   vusb_i_rspack; //  init. response acknowledge
output   [31:0] vusb_i_wdata; //  init. write data
input   [31:0] vusb_t_address; //  target address
input   [3:0] vusb_t_be; //  target byte enables
input   [1:0] vusb_t_cmd; //  target command
input   vusb_t_cmdval; //  target command valid
input   vusb_t_eop; //  target end of packet
input   vusb_t_rspack; //  target response acknowledge
input   [31:0] vusb_t_wdata; //  target write data
output   vusb_t_cmdack; //  target command acknowledge
output   [31:0] vusb_t_rdata; //  target read data
output   vusb_t_reop; //  target response end of packet
output   vusb_t_rspval; //  target response valid
output   vusb_irq; 
input   usb_rcv; 
input   usb_dp; 
input   usb_dm; 
input   usb_vbus_in; 
output   usb_dpo; 
output   usb_dmo; 
output   usb_oe_n; 
output   usb_speed; 
output   usb_suspnd; 
output   usb_dp_high; 
output   usb_dp_low_n; 
output   usb_dm_high; 
output   usb_dm_low_n; 
input   usb_id; //  id pin from mini connectors
input   usb_a_vbus_vld; //  "A" VBUS valid
input   usb_sess_vld; //  "B" session valid
input   usb_b_sess_end; //  "B" session end
output   usb_vbus_on; //  turn on vbus
output   usb_vbus_chg; //  charge vbus
output   usb_vbus_dschg; 
wire    [31:0] vusb_i_address; 
wire    [3:0] vusb_i_be; 
wire    [1:0] vusb_i_cmd; 
wire    vusb_i_cmdval; 
wire    vusb_i_eop; 
wire    vusb_i_rspack; 
//  BVCI Target Interface
wire    [31:0] vusb_i_wdata; 
wire    vusb_t_cmdack; 
wire    [31:0] vusb_t_rdata; 
wire    vusb_t_reop; 
//  interrupt out
wire    vusb_t_rspval; 
//  USB transceiver interface
wire    vusb_irq; 
wire    usb_dpo; 
wire    usb_dmo; 
wire    usb_oe_n; 
wire    usb_speed; 
//  pull-up resistor controls
wire    usb_suspnd; 
wire    usb_dp_high; 
wire    usb_dp_low_n; 
wire    usb_dm_high; 
//  OTG signals
wire    usb_dm_low_n; 
wire    usb_vbus_on; 
wire    usb_vbus_chg; 
//  discharge vbus    
wire    usb_vbus_dschg; 
wire    [43:0] cdb_in; //  Control/Data bus in
wire    [45:0] cdb_out; //  Control/Data bus out
wire    low_speed_req; //  request USB communication to low speed
wire    usb_en; //  device enable
//  fifo signals  
wire    stat_empty; //  Status FIFO empty
wire    stat_full; //  Status FIFO full
wire    [7:0] stat_rdata; //  Status FIFO read data
wire    stat_re; //  Status FIFO read enable
wire    [7:0] stat_wdata; //  Status FIFO write data
wire    stat_we; //  Rx FIFO write enable
wire    rx_empty; //  Rx FIFO empty
wire    rx_full; //  Rx FIFO full
wire    [7:0] rx_rdata; //  Rx FIFO read data
wire    rx_re; //  Rx FIFO read enable
wire    [7:0] rx_wdata; //  Rx FIFO write data
wire    rx_we; //  Rx FIFO write enable
wire    tx_empty; //  Tx FIFO empty
wire    tx_full; //  Tx FIFO full
wire    [7:0] tx_rdata; //  Tx FIFO read data
wire    tx_re; //  Tx FIFO read enable
wire    tx_valid; //  Tx FIFO has valid data in it
wire    [7:0] tx_wdata; //  Tx FIFO write data
wire    tx_we; //  Tx FIFO write enable
wire    flush; //  FIFO flush enable
//  USB Interface signals
wire    hc_en; //  USB embedded host controller enable
wire    host_mode_en; //  embedded host controller enable
wire    host_wo_hub; //  embedded host without hub control
wire    low_speed_en; //  USB Speed Indicator
wire    suspnd; //  USB Suspend
wire    usboe; //  USB Output Enable 
wire    dpo; //  USB Data Plus Output
wire    dmo; //  USB Data Minus Output
wire    rcv_data; //  USB Receive Data in
wire    rcv_nrzi; //  USB Receive Data NRZI
wire    dpi; //  USB Data Plus In
wire    dmi; //  USB Data Minus IN
//  clock enables
wire    sys_clken12; //  12MHz Clock enable output
wire    clken_dpll; //  clock enable from dpll
//  ratematch signals
wire    dpll_data; //  USB Receive Data NRZ
wire    dpll_eop; //  USB single ended zero
wire    dpll_jstate; //  USB Synchronized Jstate
wire    dpll_se0; //  USB single ended zero
wire    sie_rcv_nrz; //  USB Receive Data NRZ
wire    sie_jstate; //  USB Synchronized Jstate
wire    sie_eop; //  USB single ended zero
wire    sie_se0; //  USB single ended zero
wire    sie_clk_en; //  clock enable to SIE
wire    sie_dpo; 
wire    sie_dmo; 
wire    sie_usboe; 
wire    sie_usboe_early; 
wire    zero; 
// ---------------------------------------------------------------------------
//  code starts here
// ---------------------------------------------------------------------------

assign zero = 1'b 0; 
assign hc_en = IMPLEMENT_EMBEDED_HOST & host_mode_en; 
vusb_up_int_bvci u_vusb_up_int_bvci (	//  system signals
          .clk(clk),
          //  system clock
          .rst(rst),
          //  sync reset
          .rst_a(rst_a),
          //  async reset
          .sys_clken12(sys_clken12),
          //  12 mhz clock enable
//  BVCI Initiator Interface
          .i_cmdack(vusb_i_cmdack),
          //  init. command acknowledge
          .i_rdata(vusb_i_rdata),
          //  init. read data
          .i_reop(vusb_i_reop),
          //  init. response end of packet
          .i_rspval(vusb_i_rspval),
          //  init. response valid
          .i_address(vusb_i_address),
          //  init. address
          .i_be(vusb_i_be),
          //  init. byte enables
          .i_cmd(vusb_i_cmd),
          //  init. command
          .i_cmdval(vusb_i_cmdval),
          //  init. command valid
          .i_eop(vusb_i_eop),
          //  init. end of packet
          .i_rspack(vusb_i_rspack),
          //  init. response acknowledge
          .i_wdata(vusb_i_wdata),
          //  init. write data
//  BVCI Target Interface
          .t_address(vusb_t_address),
          //  target address
          .t_be(vusb_t_be),
          //  target byte enables
          .t_cmd(vusb_t_cmd),
          //  target command
          .t_cmdval(vusb_t_cmdval),
          //  target command valid
          .t_eop(vusb_t_eop),
          //  target end of packet
          .t_rspack(vusb_t_rspack),
          //  target response acknowledge
          .t_wdata(vusb_t_wdata),
          //  target write data
          .t_cmdack(vusb_t_cmdack),
          //  target command acknowledge
          .t_rdata(vusb_t_rdata),
          //  target read data
          .t_reop(vusb_t_reop),
          //  target response end of packet
          .t_rspval(vusb_t_rspval),
          //  target response valid
//  usb 1.1 interrupt
          .vusb_irq(vusb_irq),
          //  Control/Data bus interface
          .cdb_in(cdb_out),
          //  Control/Data bus in
          .cdb_out(cdb_in),
          //  Control/Data bus out
          .flush(flush),
          //  fifo flush
          .rcv(sie_jstate),
          //  USB data input
          .se0(sie_se0),
          //  USB single ended zero
          .host_mode_en(host_mode_en),
          //  embedded host controller enable
          .low_speed_req(low_speed_req),
          //  set USB communication to low speed
          .host_wo_hub(host_wo_hub),
          //  set USB communication to low speed
          .usb_en(usb_en),
          //  USB pull up enable
//  Status FIFO Interface
          .stat_empty(stat_empty),
          //  Status FIFO empty
          .stat_full(stat_full),
          //  Status FIFO full
          .stat_rdata(stat_rdata),
          //  Status FIFO read data
          .stat_re(stat_re),
          //  Status FIFO read enable
          .stat_we(stat_we),
          //  Status FIFO write enable
          .stat_wdata(stat_wdata),
          //  Status FIFO write data
//  RX FIFO Interface
          .rx_empty(rx_empty),
          //  Rx FIFO empty
          .rx_rdata(rx_rdata),
          //  Rx FIFO read data
          .rx_re(rx_re),
          //  Rx FIFO read enable
//  TX FIFO Interface
          .tx_full(tx_full),
          //  Tx FIFO full
          .tx_wdata(tx_wdata),
          //  Tx FIFO write data
          .tx_we(tx_we),
          //  Tx FIFO write enable
//  OTG signals
          .usb_id(usb_id),
          .usb_sess_vld(usb_sess_vld),
          .usb_a_vbus_vld(usb_a_vbus_vld),
          .usb_b_sess_end(usb_b_sess_end),
          .usb_dp_high(usb_dp_high),
          .usb_dm_high(usb_dm_high),
          .usb_dp_low_n(usb_dp_low_n),
          .usb_dm_low_n(usb_dm_low_n),
          .usb_vbus_on(usb_vbus_on),
          .usb_vbus_chg(usb_vbus_chg),
          .usb_vbus_dschg(usb_vbus_dschg));
vusb_sie u_vusb_sie (.clk(clk),
          //  Clock
          .clk_en(sie_clk_en),
          //  Clock Enable 
          .clken_12(sys_clken12),
          //  SOF timer clock enable
          .rst(rst),
          //  Synchronous reset
          .rst_a(rst_a),
          //  async reset
          .cdb_in(cdb_in),
          //  Control/Data bus in
          .cdb_out(cdb_out),
          //  Control/Data bus out
          .rx_full(rx_full),
          //  Rx FIFO full
          .rx_wdata(rx_wdata),
          //  Rx FIFO write data
          .rx_we(rx_we),
          //  Rx FIFO write enable
          .tx_empty(tx_empty),
          //  Tx FIFO empty
          .tx_rdata(tx_rdata),
          //  Tx FIFO read data
          .tx_re(tx_re),
          //  Tx FIFO read enable
          .tx_valid(tx_valid),
          //  Tx FIFO has valid data in it
          .flush(flush),
          //  FIFO flush enable
          .host_mode_en(host_mode_en),
          //  enable embbeded host functions.
          .host_wo_hub(host_wo_hub),
          //  allow a direcly connected low speed device
          .low_speed_req(low_speed_req),
          //  USB low speed request
          .low_speed_en(low_speed_en),
          //  USB Speed Control
          .suspnd(suspnd),
          //  USB Suspend
          .usboe_early(sie_usboe_early),
          //  early pulse of USB Output Enable
          .usboe(sie_usboe),
          //  USB Output Enable
          .dpo(sie_dpo),
          //  USB Data Plus Output
          .dmo(sie_dmo),
          //  USB Data Minus Output
          .rcv(sie_rcv_nrz),
          //  USB Receive Data
          .jstate(sie_jstate),
          //  synchronized jstate signal
          .eop(sie_eop),
          //  USB single ended zero
          .se0(sie_se0),
          //  USB single ended zero
          .debug());
vusb_fifo_4_1 u_statfifo (.clk(clk),
          //  everything clocks on rising edge
          .rst(rst),
          //  reset active high
          .rst_a(rst_a),
          //  async reset
          .flush(zero),
          //  never flush the status fifo
          .wr(stat_we),
          //  write a byte
          .rd(stat_re),
          //  read a byte
          .full(stat_full),
          //  1=FIFO is full
          .half_full(),
          .empty(stat_empty),
          //  1=FIFO is empty
          .out_valid(),
          .data_in(stat_wdata),
          //  data bus in
          .data_out(stat_rdata));
vusb_fifo_8_2 u_rxfifo (.clk(clk),
          //  everything clocks on rising edge
          .rst(rst),
          //  reset active high
          .rst_a(rst_a),
          //  async reset
          .flush(flush),
          //  fifo flush 
          .wr(rx_we),
          //  write a byte
          .rd(rx_re),
          //  read a byte
          .full(rx_full),
          //  1=FIFO is full
          .half_full(),
          //  1=FIFO is half full
          .empty(rx_empty),
          //  1=FIFO is empty
          .out_valid(),
          //  1=DATA_OUT has valid data in it
          .data_in(rx_wdata),
          //  data bus in
          .data_out(rx_rdata));
vusb_fifo_8_2 u_txfifo (.clk(clk),
          //  everything clocks on rising edge
          .rst(rst),
          //  reset active high
          .rst_a(rst_a),
          //  async reset
          .flush(flush),
          //  fifo flush
          .wr(tx_we),
          //  write a byte
          .rd(tx_re),
          //  read a byte
          .full(tx_full),
          //  1=FIFO is full
          .half_full(),
          //  1=FIFO is half full
          .empty(tx_empty),
          //  1=FIFO is empty
          .out_valid(tx_valid),
          //  1=DATA_OUT has valid data in it
          .data_in(tx_wdata),
          //  data bus in
          .data_out(tx_rdata));
vusb_dpllnrzi u_pll (	//  data bus in
//  Implement DPLL
          .usb_clk48(usb_clk48),
          //  48 mhz clock 
          .datain(rcv_nrzi),
          //  NRZI encoded serial data/clock in
          .dplus(dpi),
          //  USB Data plus
          .dminus(dmi),
          //  USB Data plus
          .usb_rst48(usb_rst48),
          //  sync reset
          .usb_rst48_a(usb_rst48_a),
          //  async reset
          .low_speed_en(low_speed_en),
          //  USB speed control
          .host_wo_hub(host_wo_hub),
          //  host without hub control
          .clken_dpll(clken_dpll),
          //  clock enable output
          .clken_12(),
          //  clock divided by 4 clock enable output
//  dpll outputs to ratematch
          .dataout(dpll_data),
          //  NRZ serial data out
          .eop(dpll_eop),
          //  end of packet
          .rcvout(dpll_jstate),
          //  synchronized jstate signal
          .se0(dpll_se0),
          //  single ended zero
//  inputs from ratematch
          .out180());
vusb_ratematch u_ratematch (.usb_clk48(usb_clk48),
          .usb_rst48(usb_rst48),
          .usb_rst48_a(usb_rst48_a),
          .clken_dpll(clken_dpll),
          .clk(clk),
          .rst(rst),
          .rst_a(rst_a),
          .low_speed_en(low_speed_en),
          .sys_clken12(sys_clken12),
          //  inputs from dpll
          .dpll_data(dpll_data),
          .dpll_eop(dpll_eop),
          .dpll_rcv(dpll_jstate),
          .dpll_se0(dpll_se0),
          //  outputs to sie
          .sie_clk_en(sie_clk_en),
          .sie_data(sie_rcv_nrz),
          .sie_eop(sie_eop),
          .sie_rcv(sie_jstate),
          .sie_se0(sie_se0),
          .sie_dpo(sie_dpo),
          .sie_dmo(sie_dmo),
          .sie_usboe(sie_usboe),
          .sie_usboe_early(sie_usboe_early),
          .xcvr_dpo(dpo),
          .xcvr_dmo(dmo),
          .xcvr_usboe(usboe));
assign rcv_data = usb_rcv; //  input signals
assign dpi = usb_dp; 
assign dmi = usb_dm; 
//  Port outputs
assign usb_dpo = dpo; 
assign usb_dmo = dmo; 
assign usb_oe_n = ~usboe; 
assign usb_suspnd = suspnd; 
assign usb_speed = lsdev == 1 ? 1'b 0 : 
	~low_speed_en; 
//    -- pull-up resistor controls
//    -- adding vbusn_in to these equations so that when vbus is not there, we
//    -- don't pull-up either line
//    usb_dp_high <= usb_en AND NOT hc_en AND NOT low_speed_en AND usb_vbus_in;  
//    usb_dm_high <= usb_en AND NOT hc_en AND     low_speed_en AND usb_vbus_in;
//    -- in host mode these will be low to ground pull down resistors 
//    usb_dp_low_n  <= NOT hc_en;
//    usb_dm_low_n  <= NOT hc_en;  
//  To prevent the DPLL from screwing up during tranmission mask with usboe
assign rcv_nrzi = usboe == 1'b 1 & (lsdev == 1 | 
	low_speed_en == 1'b 1) ? 1'b 0 : 
	usboe == 1'b 1 ? 1'b 1 : 
	rcv_data; 
// ---------------------------------------------------------------------------
//  component declarations
// ---------------------------------------------------------------------------

endmodule // module vusb_bvci