/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_p11
-- Date Created: Tue Jul 16 14:01:01 2002

*******************************************************************************/


`timescale 1 ns / 1 ps  // timescale for following modules

// ------------------------------------------------------------------------------
//  Copyright 1996 VAutomation Inc. Nashua NH USA ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and 
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_p11.vhd
// 
//  Description: 
//       VHDL entity for the Philips Semiconductors generic USB
//       transceiver. Only used for PCB generation.
//  Phillips Semi part # PDIUSBP11D
// 
// ---------------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   4    VUSB      1.3         4/11/02 2:49:11 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   3    VUSB      1.2         6/22/01 1:19:20 PM     Monika Leary    Changed 
//         name from vusbp11 to vusb_p11
//   2    VUSB      1.1         6/22/01 1:13:40 PM     Monika Leary    
//   1    VUSB      1.0         6/21/01 10:43:25 AM    Tom Frechette   
//  $
//  Revision 1.5  1998/05/06 21:11:16  eric
//  removed RCV driving Xes - sends noise instead.
// 
//  Revision 1.4  1997/02/20  22:01:39  chris
//  Corrected input port functions.
// 
//  Revision 1.3  1997/02/07 20:00:54  chris
//  Added greggs architecture to pass the appropriate signals.
// 
//  Revision 1.2  1996/11/11  19:55:04  eric
//  Added architecture.
// 
// ------------------------------------------------------------------------------
module vusb_p11 (oe_n,
   rcv,
   vp,
   vm,
   suspnd,
   speed,
   dminus,
   dplus,
   vpo,
   vmo,
   gnds,
   pwr);
input   oe_n; //  Ouput enable
output   rcv; //  Receive data
output   vp; //  V plus
output   vm; //  V minus
input   suspnd; //  Suspend
input   speed; //  Speed
inout   dminus; //  D minus
inout   dplus; //  D plus
input   vpo; //  Data out
input   vmo; //  Data out
input   gnds; //  Ground
input   pwr; 
wire    VHDL2V_dminus; 
wire    VHDL2V_dplus; 
wire    rcv; 
wire    vp; 
wire    vm; 
wire    dminus; 
wire    dplus; 
reg     pwron; 
wire    noise; 

initial 
   begin
   pwron <= 1'b 0;	
   #( 1000 ); 
   pwron <= 1'b 1;	
   end

assign #(321) noise = ~noise & pwron; //  321 is arbitrary
//  RCV by spec must be ignored during an SE0 as it is likely
//  that RCV will bounce around when both sides of the differential
//  receiver are at the same voltage.
//  The NOISE signal injects random transitions on the RCV signal
//  during a SE0. This is better than outputting an X because in
//  most gate level simulations the X will propagate no matter what.
//  When extracting test vectors. you may want to force
//  pwron to be 0 so that the noise signal is always 0.
//  Otherwise there will be various errors due to the asynchronous
//  NOISE signal.
assign dplus = oe_n === 1'b 0 ? vpo : 
	oe_n === 1'b 1 ? 1'b Z : 
	1'b X; 
assign dminus = oe_n === 1'b 0 ? vmo : 
	oe_n === 1'b 1 ? 1'b Z : 
	1'b X; 
//  differencial input reciever
assign rcv = (dplus === 1'b 1 | dplus === 1'b 1) & 
	(dminus === 1'b 0 | dminus === 1'b 0) ? 1'b 1 : 
	(dplus === 1'b 0 | dplus === 1'b 0) & 
	(dminus === 1'b 1 | dminus === 1'b 1) ? 1'b 0 : 
	noise; 
//  single ended input recievers
assign vp = dplus === 1'b 1 | dplus === 1'b 1 ? 1'b 1 : 
	dplus === 1'b 0 | dplus === 1'b 0 ? 1'b 0 : 
	1'b 0; 
assign vm = dminus === 1'b 1 | dminus === 1'b 1 ? 1'b 1 : 
	dminus === 1'b 0 | dminus === 1'b 0 ? 1'b 0 : 
	1'b 0; 

endmodule // module vusb_p11