/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_sie
-- Date Created: Tue Jul 16 13:58:50 2002

*******************************************************************************/


`timescale 1 ns / 1 ns // timescale for following modules

// -----------------------------------------------------------------------------
//  Copyright 1996 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_sie.vhd    VAutomation USB Serial Interface Engine
// 
//  Revision: $Revision: 1.1.1.1 $
// 
//  Description:
//   Synthesizabe VHDL description implementing the USB Serial Interface
//   Engine (SEI). 
//   
// 
//  Block Diagram:
// 
// ------------------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   127  VUSB      1.126       7/5/02 2:00:56 PM      Will Sanborn    Removed 
//         hub signals, which were not used.
//   126  VUSB      1.125       6/27/02 6:04:02 PM     Will Sanborn    Doc 
//         Change Only: replacing "synopsysTM" in comments with "_synopsysTMTM" to 
//         prevent error with compiler interpreting those comments as pragmas.
//   125  VUSB      1.124       6/27/02 3:20:12 PM     Will Sanborn    Modified 
//         outputs in ratematch block, so OE signal goes active before the data 
//         signals on DPO and DMO.
//   124  VUSB      1.123       6/25/02 2:36:13 PM     Chris Kolb      Added 
//         resume/remote wake-up detection logic.
//   123  VUSB      1.122       4/11/02 2:49:12 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   122  VUSB      1.121       2/18/02 9:02:20 AM     Tom Frechette   Added 
//         reset to rx_reg process
//   121  VUSB      1.120       2/14/02 2:32:24 PM     Tom Frechette   Moved 
//         single ended transceiver logic to sie.
//   120  VUSB      1.119       2/7/02 4:42:15 PM      Tom Frechette   Changed 
//         async to _a and sync names on reset.
//   119  VUSB      1.118       2/7/02 3:59:16 PM      Tom Frechette   Fixed 
//         corrupt handshake bug. Added pid_chk_ok to reject_tx.
//   118  VUSB      1.117       1/9/02 10:30:25 AM     Tom Frechette   Addressed
//          token done bug. If the handshake packet is corrupt, we don't report 
//         a token done.
//   117  VUSB      1.116       11/29/01 4:53:05 PM    Tom Frechette   Changed 
//         comments to _synopsysTMTM.
//   116  VUSB      1.115       10/30/01 11:01:31 AM   Monika Leary    Removed a
//          couple of unused signals to get rid of synthesis warnings
//   115  VUSB      1.114       10/2/01 11:09:10 AM    Monika Leary    Changed 
//         endpoint stall so we don't stall on a setup
//   114  VUSB      1.113       8/23/01 9:49:31 AM     Tom Frechette   
//   113  VUSB      1.112       7/24/01 5:05:51 PM     Monika Leary    Changed 
//         async reset portion of a register to get rid of a synthesis warning
//   112  VUSB      1.111       7/9/01 3:25:51 PM      Tom Frechette   Moved 
//         host only register into its own proc.
//   111  VUSB      1.110       7/9/01 2:44:45 PM      Tom Frechette   One more 
//         time for verilog trans.
//   110  VUSB      1.109       7/9/01 2:14:49 PM      Tom Frechette   Still 
//         changing comments position for verilog.
//   109  VUSB      1.108       7/9/01 1:27:43 PM      Tom Frechette   Adjusting
//          host remove comment for verilog.
//   108  VUSB      1.107       7/9/01 11:09:49 AM     Tom Frechette   Moved 
//         host remove comments for verilog translation.
//   107  VUSB      1.106       6/22/01 9:07:18 AM     Tom Frechette   Changed 
//         name of Config package
//   106  VUSB      1.105       6/21/01 10:00:30 AM    Tom Frechette   Changed 
//         the name.
//   105  VUSB      1.104       6/21/01 9:52:19 AM     Tom Frechette   
//   104  VUSB      1.103       5/25/01 10:26:28 AM    Monika Leary    Changed 
//         usboe generation so it is output from a register
//   103  VUSB      1.102       5/16/01 3:24:23 PM     Tom Frechette   Moved 
//         hc_reset to clear sof cnt outside of the clken_12 if statement.
//   102  VUSB      1.101       5/15/01 3:40:30 PM     Monika Leary    Added 
//         async reset, made all registers run on one clock, removed output 
//         registers from usboe, dpo and dmo.
//   101  VUSB      1.100       1/18/01 1:44:20 PM     Chris Kolb      Changed 
//         txd_pid_data generation from a concurrent construct to a process to 
//         try to work around a bug in exemplar.
//   100  VUSB      1.99        12/14/00 8:45:32 AM    Christopher Meyers RCS 
//         Keyword To StarTeam Keyword Translation
//   99   VUSB      1.98        12/13/00 9:15:33 PM    Chris Kolb      Changed 
//         the current_token and current endpoint, so that they would not be 
//         effected by an SOF token to prevent thrashing of the cached BDT by 
//         SOF tokens.
//   98   VUSB      1.97        12/13/00 9:15:27 PM    Mark Pettigrew  # added 
//         host_wo_hub to sensitivity list of Tx Data Packet state machine
//   97   VUSB      1.96        12/13/00 9:15:20 PM    Chris Kolb      Changed 
//         host_wo_hub from a generic to a signal. Changed architecture name to 
//         rtl.
//   96   VUSB      1.95        12/13/00 9:15:14 PM    Gregory Recupero Fixed 
//         NAK response during a SETUP token if bus_gnt lost during data phase. 
//         Also change dma_err_set for FIFO overflow and underflow conditions
//   95   VUSB      1.94        12/13/00 9:15:08 PM    Gregory Recupero Removed 
//         ^M's
//   94   VUSB      1.93        12/13/00 9:15:01 PM    Mark Pettigrew  
//         ulogicified source - no functional changes
//   93   VUSB      1.92        12/13/00 9:14:55 PM    Mark Pettigrew  fixed 
//         'reject_rx_dat_set' assertion condition - should be '/= PID_SETUP'
//   92   VUSB      1.91        12/13/00 9:14:48 PM    Chris Kolb      Changed 
//         bts_err_set so that the idle state on the bus would not be reported 
//         as a bit stuff error while waiting for a sync pulse in the TOK_SYNC 
//         state.
//   91   VUSB      1.90        12/13/00 9:14:41 PM    Mark Pettigrew  updated 
//         EMBEDDED HOST ADD section to drive 'low_speed_en'. Need to drive this
//          else usb dev mode dies.
//   90   VUSB      1.89        12/13/00 9:14:35 PM    Chris Kolb      Added 
//         term to ser2par_rg_d to prevent false syncs.
//   89   VUSB      1.88        12/13/00 9:14:28 PM    Chris Kolb      Removed 
//         reduntant assignments to low_speed_en and hc_ls_timing_set. Cleaned 
//         up sensitivity lists and unused signals.
//   88   VUSB      1.87        12/13/00 9:14:21 PM    Chris Kolb      Changed 
//         hc_ls_timing_clr to cause a PRE_PID to be generated when sending a 
//         RXD_HSHK transmit packet (IN token ACK, NAK or STALL) to a low speed 
//         device.
//   87   VUSB      1.86        12/13/00 9:14:15 PM    Chris Kolb      Added 
//         host_wo_hub generic to allow host without hub to be set individually 
//         for each vusb core is a simulation.
//   86   VUSB      1.85        12/13/00 9:14:09 PM    Chris Kolb      Added 
//         logic to support Low speed devices thru a hub.
//   85   VUSB      1.84        12/13/00 9:14:02 PM    Chris Kolb      Added hc 
//         (host control) reset to reset the state machines when host mode is 
//         entered or exited.
//   84   VUSB      1.83        12/13/00 9:13:55 PM    Chris Kolb      Added 
//         support for SOF timer function for LS host. Fixed bug with Frame 
//         number loading.
//   83   VUSB      1.82        12/13/00 9:13:49 PM    Chris Kolb      Cut the 
//         response turnaround time by one cycle to give customers more margin 
//         when running gate level simulation.
//   82   VUSB      1.81        12/13/00 9:13:43 PM    Chris Kolb      Fixed 
//         crc5_err_set by removing not TOK_EOP term from the ser2par_rg_se 
//         equation. Extended the range of the DFN8 error indication to cover 
//         any packet that token, data or handshake that ends on a non-byte 
//         boundary.
//   81   VUSB      1.80        12/13/00 9:13:35 PM    Chris Kolb      Fixed 
//         signal exchange problems associated with low speed host operation.
//   80   VUSB      1.79        12/13/00 9:13:29 PM    Gregory Recupero Modified
//          output signal generation to use the low_speed_dev constant to 
//         generate low speed signaling.
//   79   VUSB      1.78        12/13/00 9:13:23 PM    Chris Kolb      Added a 
//         cycle of delay to sie_eop_out to support tighter connection tear down
//          timing in the hub.
//   78   VUSB      1.77        12/13/00 9:13:17 PM    Chris Kolb      Changed 
//         clear pulse on SOF counter from the asynchronous mcek_cnt_clr to the 
//         synchronized sof_cnt_clr. This effected the sleep interrupt 
//         generation.
//   77   VUSB      1.76        12/13/00 9:13:11 PM    Chris Kolb      Recoded 
//         inputs and outputs of hc_sof_cnt with the clock enable crossings in 
//         mind.
//   76   VUSB      1.75        12/13/00 9:13:05 PM    Chris Kolb      Fixed 
//         width of hc_sof_cnt constant compare in frame_num_d equation.
//   75   VUSB      1.74        12/13/00 9:12:59 PM    Chris Kolb      Changed 
//         _synopsysTM(TM) comment placement so it would survive translation to 
//         verilog.
//   74   VUSB      1.73        12/13/00 9:12:53 PM    Chris Kolb      Added 
//         synchronous reset term for own_ok_suspend.
//   73   VUSB      1.72        12/13/00 9:12:47 PM    Chris Kolb      Fixed 
//         vasync comment on rx_srst_regs process.
//   72   VUSB      1.71        12/13/00 9:12:41 PM    Chris Kolb      Fixed 
//         token busy.
//   71   VUSB      1.70        12/13/00 9:12:35 PM    Gregory Recupero Added 
//         resume support for device and host controller modes
//   70   VUSB      1.69        12/13/00 9:12:28 PM    Chris Kolb      Added 
//         logic to make ISO packet tokens ignore the txd suspend signal.
//   69   VUSB      1.68        12/13/00 9:12:22 PM    Chris Kolb      Removed a
//          cycle ofdelay from the BDT endpoint stall indication, so that it 
//         would track the BDT OWN bit.
//   68   VUSB      1.67        12/13/00 9:12:16 PM    Chris Kolb      Added 
//         code to suspend any transfer type when txd_suspend is true. Change 
//         assertion of txd_suspend to occur when a SETUP token is completed. 
//         Added code to cause BDT's not to be cached when txd_suspend is true.
//   67   VUSB      1.66        12/13/00 9:12:09 PM    Gregory Recupero Added 
//         suspend timer and sleep logic
//   66   VUSB      1.65        12/13/00 9:12:03 PM    Chris Kolb      Added 
//         hardware dequeuing and protocol stall support.
//   65   VUSB      1.64        12/13/00 9:11:56 PM    Chris Kolb      False 
//         bitstuff error detect at end of packet fix.
//   64   VUSB      1.63        12/13/00 9:11:50 PM    Chris Kolb      Added 
//         code to suppress the token done interrupt and BDT write, but flush 
//         any remaining data at the end of packet if the KEEP bit is set.
//   63   VUSB      1.62        12/13/00 9:11:43 PM    Chris Kolb      Changed 
//         sie_eop_out output to assert for one cycle after the SE0 to J 
//         transition. ;
//   62   VUSB      1.61        12/13/00 9:11:36 PM    Chris Kolb      Removed 8
//          cycle time limit in TOK_SYNC state to allow sync detection even if 
//         the PLL adjusts short twice in response to a slow clock with a phase 
//         shift.
//   61   VUSB      1.60        12/13/00 9:11:29 PM    Chris Kolb      Added 
//         acknowledge for token req and clr from up_int.
//   60   VUSB      1.59        12/13/00 9:11:22 PM    Chris Kolb      Recoded 
//         for synchronous reset.
//   59   VUSB      1.58        12/13/00 9:11:15 PM    Gregory Recupero Updated 
//         HOST ADD for Makerelease
//   58   VUSB      1.57        12/13/00 9:11:09 PM    Chris Kolb      Moved SOF
//          timer and associated logic to a fixed 12MHz clock enable.
//   57   VUSB      1.56        12/13/00 9:11:03 PM    Chris Kolb      Added 
//         syntax for Async or Sync reset inference.
//   56   VUSB      1.55        12/13/00 9:10:56 PM    Chris Kolb      Syntax 
//         error.
//   55   VUSB      1.54        12/13/00 9:10:49 PM    Chris Kolb      Added 
//         signals for VUSB Hub. Added logic to support cancelling host tokens.
//   54   VUSB      1.53        12/13/00 9:10:42 PM    Chris Kolb      Fixed 
//         false BTS error generation during RXD_EOP.
//   53   VUSB      1.52        12/13/00 9:10:34 PM    Chris Kolb      Changed 
//         logic so ISO in tokens that BTO will be sent only once.
//   52   VUSB      1.51        12/13/00 9:10:28 PM    Chris Kolb      Fixed 
//         process sensitivity lists.
//   51   VUSB      1.50        12/13/00 9:10:21 PM    Chris Kolb      Fixed 
//         host bdt reread equation after rejected rx or tx packets.
//   50   VUSB      1.49        12/13/00 9:10:14 PM    Chris Kolb      Fixed 
//         bitstuff error detection on the last bit of a packet.
//   49   VUSB      1.48        12/13/00 9:10:08 PM    Chris Kolb      Added 
//         error condition handling for bit_stuff, DFN8, Premature EOP, CRC5, 
//         CRC16 Data fifo over and underrun, endpoint stall, data toggle 
//         synchronization, and owns bit latency.
//   48   VUSB      1.47        12/13/00 9:10:02 PM    Chris Kolb      Added 
//         code to support bit stuff generation on the last bit of a token 
//         packet. Simplified the attach interrupt hardware. Added support for 
//         longer latency memory systems (BDT caching).
//   47   VUSB      1.46        12/13/00 9:09:55 PM    Chris Kolb      Corrected
//          Host token operation.
//   46   VUSB      1.45        12/13/00 9:09:49 PM    Gregory Recupero Fixed 
//         erroneous bts_err_set during high performance mode operation
//   45   VUSB      1.44        12/13/00 9:09:43 PM    Chris Kolb      Enabled 
//         and debugged host mode operations.
//   44   VUSB      1.43        12/13/00 9:09:35 PM    Chris Kolb      Added 
//         code to support embedded host mode operations. Currently untested.
//   43   VUSB      1.42        12/13/00 9:09:28 PM    Chris Kolb      Changed 
//         the meaning of the endpoint control register bit definitions.
//   42   VUSB      1.41        12/13/00 9:09:22 PM    Chris Kolb      Added 
//         clock enable to logic to all registers and strobed outputs.
//   41   VUSB      1.40        12/13/00 9:09:17 PM    Chris Kolb      Removed 
//         <Control-M> characters from the line ends.
//   40   VUSB      1.39        12/13/00 9:09:10 PM    Gregory Recupero Added 
//         additional error support
//   39   VUSB      1.38        12/13/00 9:09:05 PM    Chris Kolb      Removed 
//         transition that rejected packets that have long EOP pulses.
//   38   VUSB      1.37        12/13/00 9:08:59 PM    Eric Ryherd     chenged 
//         the DET_SYNC to only check for 3 zeroes and a one instead of 6 zeros 
//         and a one which fails in the lab. PLL may blow the second bit.
//   37   VUSB      1.36        12/13/00 9:08:53 PM    Gregory Recupero Fix last
//          bit stuff of CRC
//   36   VUSB      1.35        12/13/00 9:08:48 PM    Gregory Recupero Added 
//         better se0 detection to the TOKEN state machine
//   35   VUSB      1.34        12/13/00 9:08:42 PM    Gregory Recupero Added 
//         error checking conditions
//   34   VUSB      1.33        12/13/00 9:08:36 PM    Gregory Recupero Fixed 
//         transmit of small packets
//   33   VUSB      1.32        12/13/00 9:08:30 PM    Gregory Recupero Added 
//         direction support to bulk and iso endpoints
//   32   VUSB      1.31        12/13/00 9:08:23 PM    Gregory Recupero Fixed 
//         otk_pstate to use ser2par_cnt_eq7 Added enumerated type variables for
//          simulation debug
//   31   VUSB      1.30        12/13/00 9:08:17 PM    Gregory Recupero Added 
//         new endpoint control register formats
//   30   VUSB      1.29        12/13/00 9:08:10 PM    Gregory Recupero Added 
//         EOP to the DPLL and brought more debugging signals out.
//   29   VUSB      1.28        12/13/00 9:08:03 PM    Gregory Recupero Moved 
//         SE0 detect to DPLL.
//   28   VUSB      1.27        12/13/00 9:07:57 PM    Gregory Recupero Encoded 
//         in and out token state machines
//   27   VUSB      1.26        12/13/00 9:07:50 PM    Gregory Recupero 
//         Re-ordered Control/Data bus bit definitions
//   26   VUSB      1.25        12/13/00 9:07:43 PM    Chris Kolb      Reversed 
//         the bit order of the address comparitor input.
//   25   VUSB      1.24        12/13/00 9:07:36 PM    Gregory Recupero Added 
//         token state machine present state bit to debug bus Implemented 
//         additional error conditions CRC5_ERR, and CRC16_ERR
//   24   VUSB      1.23        12/13/00 9:07:29 PM    Gregory Recupero Improved
//          SYNC field detection
//   23   VUSB      1.22        12/13/00 9:07:22 PM    Eric Ryherd     reset the
//          ODD bits when indicated.
//   22   VUSB      1.21        12/13/00 9:07:16 PM    Gregory Recupero Added 
//         dma_early_req to reduce bus request latency
//   21   VUSB      1.20        12/13/00 9:07:10 PM    Gregory Recupero Added 
//         code for DMA_ERR on IN tokens
//   20   VUSB      1.19        12/13/00 9:07:04 PM    Gregory Recupero Added 
//         cdb signals for error status interrupts
//   19   VUSB      1.18        12/13/00 9:06:58 PM    Gregory Recupero 
//         Corrected stalled conditions of SETUP, IN, and OUT tokens for control
//          endpoints
//   18   VUSB      1.17        12/13/00 9:06:51 PM    Gregory Recupero Fixed 
//         false single ended 0 dectects
//   17   VUSB      1.16        12/13/00 9:06:45 PM    Gregory Recupero Added 
//         det_se0 and ser2par_cnt to out token statemachine sensitivity list
//   16   VUSB      1.15        12/13/00 9:06:38 PM    Gregory Recupero Fixed 
//         OUT token NAK response problem Improved false EOP rejection
//   15   VUSB      1.14        12/13/00 9:06:32 PM    Gregory Recupero 
//         Increased bus turnaround time by 2 clocks Fixed IN token with 0 byte 
//         count
//   14   VUSB      1.13        12/13/00 9:06:25 PM    Gregory Recupero Fixed 
//         BDT DATA01 writeback problem on SETUP and OUT TOKENS
//   13   VUSB      1.12        12/13/00 9:06:19 PM    Gregory Recupero Added 
//         in_handshake_done to sensitivity list
//   12   VUSB      1.11        12/13/00 9:06:13 PM    Gregory Recupero Added 
//         CRC16 and fixed bitstuff on IN tokens
//   11   VUSB      1.10        12/13/00 9:06:07 PM    Gregory Recupero Fixed IN
//          token handshake with own=0
//   10   VUSB      1.9         12/13/00 9:06:01 PM    Gregory Recupero Added IN
//          token
//   9    VUSB      1.8         12/13/00 9:05:54 PM    Gregory Recupero Added Tx
//          FIFO interface
//   8    VUSB      1.7         12/13/00 9:05:48 PM    Gregory Recupero Added Rx
//          FIFO interface
//   7    VUSB      1.6         12/13/00 9:05:41 PM    Gregory Recupero Added 
//         ser2par_cnt_eq2 to sensitivity list
//   6    VUSB      1.5         12/13/00 9:05:34 PM    Gregory Recupero Fixed 
//         bit stuff removal problem on back-to-back tokens
//   5    VUSB      1.4         12/13/00 9:05:28 PM    Gregory Recupero Added 
//         handshake states
//   4    VUSB      1.3         12/13/00 9:05:23 PM    Eric Ryherd     Fixed 
//         USB_RST_EN_D. needed to be=1 on SRST, not 0.
//   3    VUSB      1.2         12/13/00 9:05:18 PM    Gregory Recupero OUT and 
//         SETUP coded.
//   2    VUSB      1.1         12/13/00 9:05:12 PM    Chris Kolb      Added 
//         dummy assignments for unimplemented outputs.
//   1    VUSB      1.0         12/13/00 9:05:07 PM    Chris Kolb      initial 
//         revision
//  $
// ------------------------------------------------------------------------------
//  use ieee.std_logic_arith.all;
// ------------------------------------------------------------------------------
//  Copyright 1995 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and 
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_cfg.vhd	USB Configuration file.
// 
//  Revision: $Revision: 1.1.1.1 $
// 
//  Description: A Package file for the usb core that defines global usb constants
//      that contol how the VUSB core is synthesised.
// 
// ---------------------------------------------------------------------------
//  This product is licensed to:
//  $name$ of $company$
//  for use at site(s): 
//  $site$
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   32   VUSB      1.31        7/5/02 9:15:50 AM      Chris Kolb      Moved 
//         VUSB build configruation Revision constant to vusb_cfg, and updated 
//         the rev number to 3.0.
//   31   VUSB      1.30        4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   30   VUSB      1.29        3/18/02 10:52:11 AM    Tom Frechette   Changed 
//         IRQ_NUM default to 0x0.
//   29   VUSB      1.28        3/15/02 2:39:08 PM     Tom Frechette   Added 
//         Interupt info into add_info register.
//   28   VUSB      1.27        2/7/02 4:49:00 PM      Tom Frechette   Removed 
//         sync config variable.
//   27   VUSB      1.26        8/23/01 9:48:58 AM     Tom Frechette   
//   26   VUSB      1.25        7/25/01 3:41:35 PM     Tom Frechette   Changed 
//         FIFO Parameter Names.
//   25   VUSB      1.24        7/10/01 3:03:41 PM     Tom Frechette   Moved 
//         HOST comment for verilog.
//   24   VUSB      1.23        7/6/01 7:44:00 AM      Tom Frechette   Added 
//         host comments around host constant to make it look like vusb_sie.
//   23   VUSB      1.22        7/6/01 7:34:33 AM      Tom Frechette   Added 
//         device constant comment for ARC.
//   22   VUSB      1.21        7/3/01 4:42:08 PM      Tom Frechette   Changed 
//         mode to a constant in vusb_cfg.
//   21   VUSB      1.20        6/22/01 3:09:48 PM     Tom Frechette   Changed 
//         endpoint number.
//   20   VUSB      1.19        6/21/01 9:59:56 AM     Tom Frechette   Changed 
//         the name and added fifo constants
//   19   VUSB      1.18        6/21/01 9:51:24 AM     Tom Frechette   
//   18   VUSB      1.17        5/25/01 10:25:08 AM    Monika Leary    Set 
//         synchronous reset constant to '1'
//   17   VUSB      1.16        5/17/01 2:52:48 PM     Monika Leary    Added 
//         USE_SYNC_RESET constant
//   16   VUSB      1.15        12/14/00 8:42:11 AM    Christopher Meyers RCS 
//         Keyword To StarTeam Keyword Translation
//   15   VUSB      1.14        12/13/00 7:58:39 PM    Chris Kolb      Removed 
//         the HOST_WITHOUT_HUB constant. This control is now a Endpt0 control 
//         register bit in up_int.vhd.
//   14   VUSB      1.13        12/13/00 7:58:31 PM    Gregory Recupero Removed 
//         ^M's
//   13   VUSB      1.12        12/13/00 7:58:26 PM    Mark Pettigrew  
//         ulogicified source - no functional changes
//   12   VUSB      1.11        12/13/00 7:58:19 PM    Chris Kolb      Change 
//         type of HOST_WITHOUT_HUB from std_logic to integer so that it could 
//         be used to initialize a _synopsysTM(TM) compatible generic.
//   11   VUSB      1.10        12/13/00 7:58:14 PM    Chris Kolb      Set 
//         constant to support Host to Low Speed device thru a hub.
//   10   VUSB      1.9         12/13/00 7:58:07 PM    Chris Kolb      Changed 
//         LOW_SPEED_DEV constant to type integer to support generics.
//   9    VUSB      1.8         12/13/00 7:57:58 PM    Christopher Meyers 
//         removed ASIC_IMPLEMENTATION constant
//   8    VUSB      1.7         12/13/00 7:57:46 PM    Chris Kolb      Remove 
//         ^M's. No functional changes.
//   7    VUSB      1.6         12/13/00 7:57:39 PM    Chris Kolb      Added 
//         HOST_WITHOUT_HUB constant to support new code in the DPLLNRZI.
//   6    VUSB      1.5         12/13/00 7:57:19 PM    Chris Kolb      Turned 
//         host mode back on.
//   5    VUSB      1.4         12/13/00 7:57:12 PM    Chris Kolb      Reverted 
//         to device only implementation.
//   4    VUSB      1.3         12/13/00 7:57:08 PM    Chris Kolb      Added 
//         revision string.
//   3    VUSB      1.2         12/13/00 7:57:03 PM    Chris Kolb      Enabled 
//         implementation of embedded host functions.
//   2    VUSB      1.1         12/13/00 7:56:58 PM    Chris Kolb      Added 
//         IMPLEMENT_EMBEDED_HOST constant.
//   1    VUSB      1.0         12/13/00 7:56:51 PM    Chris Kolb      initial 
//         revision
//  $
// 
// 
// ------------------------------------------------------------------------------
module vusb_sie (clk,
   clk_en,
   clken_12,
   rst,
   rst_a,
   cdb_in,
   cdb_out,
   rx_full,
   rx_wdata,
   rx_we,
   tx_empty,
   tx_rdata,
   tx_re,
   tx_valid,
   flush,
   host_mode_en,
   host_wo_hub,
   low_speed_req,
   low_speed_en,
   suspnd,
   usboe_early,
   usboe,
   dpo,
   dmo,
   rcv,
   jstate,
   eop,
   se0,
   debug);

 		// file containing translation of VHDL package 'vusb_cfg' 

parameter lsdev = 0;
`include "vusb_cfg.v"
input   clk; //  Clock
input   clk_en; //  Clock enable
input   clken_12; //  SOF timer clock enable
input   rst; //  Reset synchronous
input   rst_a; //  reset asynchronous
input   [43:0] cdb_in; //  Control/Data bus in
output   [45:0] cdb_out; //  Control/Data bus out
input   rx_full; //  Rx FIFO full
output   [7:0] rx_wdata; //  Rx FIFO write data
output   rx_we; //  Rx FIFO write enable
input   tx_empty; //  Tx FIFO empty
input   [7:0] tx_rdata; //  Tx FIFO read data
output   tx_re; //  Tx FIFO read enable
input   tx_valid; //  Tx FIFO has valid data in it
output   flush; //  FIFO flush enable
input   host_mode_en; //  enable embedded host if implemented
input   host_wo_hub; //  host without hub control
input   low_speed_req; //  USB Speed Control from uProc
output   low_speed_en; //  USB Speed Control to DPLL
output   suspnd; //  USB Suspend
output   usboe_early; //  early pulse of USB Output Enable
output   usboe; //  USB Output Enable
output   dpo; //  USB Data Plus Output
output   dmo; //  USB Data Minus Output
input   rcv; //  USB Receive Data
input   jstate; //  synchronized jstate signal
input   eop; //  USB end of packet
input   se0; //  USB single ended zero
output   [15:0] debug; //  Debug bus
wire    [45:0] cdb_out; 
wire    [7:0] rx_wdata; 
wire    rx_we; 
wire    tx_re; 
wire    flush; 
wire    low_speed_en; 
wire    suspnd; 
wire    usboe_early; 
wire    usboe; 
wire    dpo; 
wire    dmo; 
wire    [15:0] debug; 
parameter SUSPEND_TERM_CNT_HS = {4'b 1000, 4'b 1100, 4'b 1010, 4'b 0000}; //  8ca0h = 36,000
parameter SUSPEND_TERM_CNT_LS = {4'b 0001, 
	4'b 0001, 4'b 1001, 4'b 0100}; //  1194h = 4,500
parameter SOF_TERM_CNT_HS = {4'b 0010, 4'b 1110, 
	4'b 1101, 4'b 1111}; //  2ee0h = 12,000
// "0000" & "0100" & "0110" & "0000"; -- 0460h = 1,200
parameter SOF_TERM_CNT_LS = {4'b 0000, 4'b 0101, 4'b 1101, 
	4'b 1100}; //  05dch = 1,500
parameter PID_OUT = 4'b 0001; 
parameter PID_IN = 4'b 1001; 
parameter PID_SOF = 4'b 0101; 
parameter PID_SETUP = 4'b 1101; 
parameter PID_DATA0 = 4'b 0011; 
parameter PID_DATA1 = 4'b 1011; 
parameter PID_ACK = 4'b 0010; 
parameter PID_NAK = 4'b 1010; 
parameter PID_STALL = 4'b 1110; 
parameter PID_PRE = 4'b 1100; 

// TYPE tok_states:
parameter tok_states_ERROR_E = 0;
parameter tok_states_TOK_IDLE_E = 1;
parameter tok_states_TOK_SYNC_E = 2;
parameter tok_states_TOK_PID_E = 3;
parameter tok_states_TOK_BYTE0_E = 4;
parameter tok_states_TOK_BYTE1_E = 5;
parameter tok_states_TOK_EOP_E = 6;
parameter tok_states_TOK_PROC_E = 7;
parameter tok_states_TOK_WAIT_E = 8;

parameter TOK_IDLE = 3'b 000; 
parameter TOK_SYNC = 3'b 001; 
parameter TOK_PID = 3'b 011; 
parameter TOK_BYTE0 = 3'b 010; 
parameter TOK_BYTE1 = 3'b 110; 
parameter TOK_EOP = 3'b 111; 
parameter TOK_PROC = 3'b 101; 
parameter TOK_WAIT = 3'b 100; 

// TYPE txd_states:
parameter txd_states_TXD_WAIT_E = 0;
parameter txd_states_TXD_SYNC_E = 1;
parameter txd_states_TXD_PID_E = 2;
parameter txd_states_TXD_DATA_E = 3;
parameter txd_states_TXD_CRC16L_E = 4;
parameter txd_states_TXD_CRC16H_E = 5;
parameter txd_states_TXD_LBS_E = 6;
parameter txd_states_TXD_EOP_E = 7;
parameter txd_states_TXD_HSHK_E = 8;
parameter txd_states_TXD_DONE_E = 9;
parameter txd_states_TXD_PRE_E = 10;
parameter txd_states_TXD_LSDLY_E = 11;
parameter txd_states_TXD_DELAY_E = 12;

parameter TXD_WAIT = 4'b 0000; 
parameter TXD_SYNC = 4'b 0001; 
parameter TXD_PID = 4'b 0010; 
parameter TXD_DATA = 4'b 0011; 
parameter TXD_CRC16L = 4'b 0100; 
parameter TXD_CRC16H = 4'b 0101; 
parameter TXD_LBS = 4'b 1110; 
parameter TXD_EOP = 4'b 0110; 
parameter TXD_HSHK = 4'b 0111; 
parameter TXD_DONE = 4'b 1000; 
parameter TXD_DELAY = 4'b 1001; 
parameter TXD_PRE = 4'b 1010; 
parameter TXD_LSDLY = 4'b 1011; 

// TYPE rxd_states:
parameter rxd_states_RXD_WAIT_E = 0;
parameter rxd_states_RXD_SYNC_E = 1;
parameter rxd_states_RXD_IDLE_E = 2;
parameter rxd_states_RXD_PID_E = 3;
parameter rxd_states_RXD_BYTE0_E = 4;
parameter rxd_states_RXD_BYTE1_E = 5;
parameter rxd_states_RXD_BYTE2_E = 6;
parameter rxd_states_RXD_EOP_E = 7;
parameter rxd_states_RXD_HSHK_E = 8;
parameter rxd_states_RXD_DONE_E = 9;

parameter RXD_WAIT = 4'b 0000; 
parameter RXD_IDLE = 4'b 0001; 
parameter RXD_SYNC = 4'b 0010; 
parameter RXD_PID = 4'b 0011; 
parameter RXD_BYTE0 = 4'b 0100; 
parameter RXD_BYTE1 = 4'b 0101; 
parameter RXD_BYTE2 = 4'b 0110; 
parameter RXD_EOP = 4'b 0111; 
parameter RXD_HSHK = 4'b 1000; 
parameter RXD_DONE = 4'b 1001; 
//  The following line is used when translating to Verilog...
//  _synopsys sync_set_reset "rst"
//  Requires the sync_set/reset attribute to insure no Xes in simulation
wire    bdt_stall_d; //  BDT stall control bit
wire    bdt_valid; //  BDT registers contain a valid BDT
wire    [3:0] bdt_wrt_pid; //  PID value for BDT
wire    bto_err_set; //  Bus timeout error interrupt set
wire    byte_count_eq; //  DMA byte count equals saved byte count
//  SIE counter signals
reg     [4:0] mcek_cnt; //  multi purpose counter
wire    mcek_cnt_clr; //  Counter clear term
reg     se0_f; //  registered copy of se0 input
reg     jstate_f; //  registered copy of rcv input
reg     [4:0] crc5_data; //  CRC5 data
wire    crc5_data_clr; //  CRC5 data load enable
wire    crc5_data_ld; //  CRC5 data load enable
wire    crc5_data_se; //  CRC5 data shift enable
wire    crc5_okay; //  CRC5 okay
wire    crc5_err_set; //  CRC5 okay
reg     [15:0] crc16_data; //  CRC16 data
wire    crc16_data_comp; //  CRC16 data compute enable
wire    crc16_data_se; //  CRC16 data shift enable
wire    [15:0] comp_crc16_data; //  Compute CRC16 data
wire    crc16_data_ld; //  CRC16 data load enable
wire    crc16_err_set; //  CRC16 error detected.
wire    crc16_okay; //  CRC16 okay
//  Current token register, token write data, and load enable
reg     [3:0] current_token; 
reg     current_token_eq; 
wire    [3:0] current_token_d; 
wire    current_token_ld; 
//  Current endpoint register, endpoint write data, and load enable
reg     [3:0] current_endpt; 
reg     current_endpt_eq; 
wire    [3:0] current_endpt_d; 
wire    current_endpt_ld; 
wire    data01; //  BDT data0/1 control bit
wire    det_rst; //  Detect USB reset
wire    det_eop; //  Detect end of packet
wire    det_se0; //  Detect single ended zero
wire    det_sync; //  Detect SYNC
reg     dev_dma_rd_bdt; //  DMA read BDT (4 bytes) (non-host)
wire    dma_rd_bdt; //  DMA read BDT (4 bytes)
reg     dma_re_rd_bdt; //  DMA re_rd BDT (4 bytes)
reg     dma_wrt_bdt; //  DMA write BDT (4 bytes)
reg     dfn8_err_tok; //  Token packet not 8-bits error interrupt set
reg     dfn8_err_rxd; //  Data field not 8-bits error interrupt set
wire    dts; //  BDT dts control bit
//  DMA early req
parameter enable_early_req = 1'b 0; 
// signal endpt_en         : std_ulogic; -- Endpoint enabled
reg     endpt_in_en; //  Endpoint rx in enabled
wire    endpt_in_en_d; //  Endpoint rx in enabled data
reg     endpt_ctl_dis; //  Endpoint not control enpoint
wire    endpt_ctl_dis_d; //  Endpoint not control enpoint
reg     endpt_out_en; //  Endpoint rx out enabled
wire    endpt_out_en_d; //  Endpoint rx out enabled data
wire    endpt_stall; //  Endpoint stall
reg     endpt_stall_clr; //  Endpoint stall clear
wire    endpt_stall_set; //  Endpoint stall set
reg     endpt_hshk; //  Endpoint handshake enable
wire    endpt_hshk_d; //  Endpoint handshake data
//  Current frame number register, frame number write data, and load enable
reg     [10:0] frame_num; 
wire    [10:0] frame_num_d; 
reg     frame_num_ld; 
//  Embedded host controller signals
wire    hc_en; //  embedded host controller functions are
//  implemented and turned on
wire    hc_en_f; 
//  edge of hc_en.
reg     hc_en_fq; //  register for  capturing the rising
wire    hc_attach_set; //  attach / detach interrupt pulse
wire    hc_det_attach; //  host controller attach detect
wire    hc_resume_set; //  attach / detach interrupt pulse
wire    hc_det_resume; //  host controller attach detect
reg     hc_dma_rd_bdt_q; //  DMA read BDT (4 bytes) (host)
wire    hc_dma_rd_bdt; //  DMA read BDT (4 bytes) (host)
wire    hc_reset; //  reset on entering or exiting host mode.
wire    hc_rst_req; //  USB reset request
// signal hc_sof_cnt_q  : std_ulogic_vector(15 downto 0); -- SOF Threshold 
reg     sof_cnt_clr0; //  SOF counter clear in clken_dpll domain
reg     sof_cnt_clra; //  two cycle wide async sof cnt clear
reg     sof_cnt_clr; //  SOF cnt clr in clken_12 domain
wire    hc_ls_timing; //  host is using low speed timing
reg     hc_ls_timing_q; //  host is using low speed timing
wire    hc_ls_timing_clr; //  finish host low speed timing
wire    hc_ls_timing_set; //  start host low speed timing
reg     tok_ls_timing_set; //  start host token low speed timing
reg     txd_ls_timing_set; //  start host txd low speed timing
wire    hc_no_retry; //  host retry not allowed on this failure
wire    hc_retry_disable; //  host retry disabled from uProcessor int
wire    [3:0] hc_rxd_pid; //  Rx PID value
reg     [3:0] hc_rxd_pid_q; //  Rx PID value
reg     [15:0] hc_sof_cnt; //  SOF Threshold 
reg     hc_sof_tc; //  SOF terminal count
wire    hc_sof_thld_set; //  SOF Threshold det interrupt pulse
wire    hc_sof_err_set; //  Start of Frame error interrupt pulse
wire    hc_sof_req; //  USB SOF transaction request
wire    hc_sof_req_set; //  USB SOF sync to clk_en
reg     hc_sof_req_set_q; //  USB SOF sync to clk_en
wire    hc_sof_req_f; //  USB SOF one clk_en delayed
reg     hc_sof_req_fq; //  USB SOF one clk_en delayed reg output
reg     hc_sof_req_q; //  USB SOF register output
wire    [7:0] hc_sof_thld; //  SOF Threshold  
wire    hc_stall_set; //  stall interrupt pulse
wire    hc_token_busy; //  the last host token request is not complete
wire    hc_token_busy_f; //  registered copy
reg     hc_token_busy_fq; //  flip_flop q output
reg     hc_token_done; //  USB token transaction completed
wire    [3:0] hc_token_endpt; //  host End Point
wire    hc_token_inhibit; //  USB token inhibit
reg     hc_token_inhibit_dq; //  token inhibit async to clke_en
wire    hc_token_inhibit_d; //  token inhibit regster input.
wire    hc_token_inhibit_f; //  USB token inhibit one cycle delayed
reg     hc_token_inhibit_fq; //  register output
reg     hc_token_inhibit_q; //  register output.
wire    hc_token_req; //  USB token transaction req
wire    [3:0] hc_token_pid; //  host PID
wire    [7:0] hc_txd_byte; //  host data byte
wire    [10:0] hc_tx_data; //  host data
reg     idpo; //  Internal USB Data plus output
wire    idmo_d; //  Internal USB Data minus output
wire    idpo_d; //  Internal USB Data plus output
wire    in_handshake_en; //  In handshake enable
reg     in_handshake_done; //  In handshake done
wire    tx_datpkt_proc; //  Tx Data Packet process
wire    tx_datpkt_done; //  Tx Data Packet process done
wire    tx_fif_re; //  internal  copy of Tx FIFO read enable
reg     [3:0] txd_pid_data; //  Tx Data Packet pid data
wire    usb_dout; //  USB data dout
wire    usb_jstate_req; //  USB jstate output request
wire    usb_kstate_req; //  USB kstate output request
wire    usb_nrzo; //  USB nrz encoded data out.
wire    usb_se0_req; //  USB single ended zero output request
//  Tx Data Packet state machine state bits
reg     [3:0] txd_enum; //  Tx Data Packet state enumerated type
reg     [3:0] txd_pstate; //  Present state bits
reg     [3:0] txd_nstate; //  Next state bits
wire    txd_token; //  the current token requires a tx data packet.
wire    txd_suspend; //  This signal is set on receipt of a SETUP
//  token and inhibits any IN token
//  processing until it is cleared by software.
reg     txd_suspend_set; //  set signal receipt of a SETUP
//  target mode transmit suspend / host mode token busy dual use signal
wire    txdsuspend_tokbusy; //  register
wire    txdsuspend_tokbusy_clr; //  clear from usb_sie
wire    txdsuspend_tokbusy_set; //  set from usb_sie
reg     txd_usboe; //  usboe from transmit state machine
wire    last_bit_stuff_en; //  Last bit stuff enable
wire    [15:0] nxt_crc16_data; //  Next CRC16 data
wire    [4:0] nxt_crc5_data; //  Next CRC5 data
//  Bit stuff logic signals
wire    bts_err_set; //  bit stuff error set signal
reg     bit_stuff_err; //  bit stuff error in this packet
reg     [2:0] one_bit_cnt; //  One bit count
wire    [2:0] one_bit_cnt_d; //  One bit count data
wire    one_bit_cnt_ld; //  One bit count load enable
wire    zero_stuff; //  This bit is a stuff bit.
wire    force_bit_stuff_err; //  Force a bit stuff error on output
reg     zero_stuff_inhibit; //  Turn off bit stuffing for one byte 
reg     out_data01_pid; //  Out data01 pid register
wire    out_data01_pid_d; //  Out data01 pid register data
wire    out_handshake_en; //  Out handshake enable
reg     out_handshake_done; //  Out handshake done
wire    resume_req; //  Assert resume signaling request
//  Rx Data Packet state machine state bits
reg     [3:0] rxd_enum; //  Rx Data Packet enumerated type
// signal rxd_nstate     : rxd_states; -- Next state bits
reg     [3:0] rxd_pstate; //  Present state bits
reg     [3:0] rxd_nstate; //  Next state bits
wire    rx_datpkt_proc; //  Rx Data Packet process
wire    rx_datpkt_done; //  Rx Data Packet process done
wire    rx_fif_we; //  Receive FIFO write enable
reg     rx_overrun_nak; //  Force a Nak responce to this Rx Packet
reg     own; //  BDT own control bit
wire    own_d; //  BDT own control bit data
wire    own_ld; //  BDT own control bit load enable
wire    own_ok; //  BDT own control bit is still valid
reg     own_ok_suspend; //  Don't cache the BDT own control bit 
//  Parallel to serial register signals
reg     [7:0] par2ser_rg; 
wire    [7:0] par2ser_rg_d; 
wire    par2ser_rg_se; //  Par2ser reg shift enable
wire    par2ser_rg_ld; //  Par2ser reg load enable
wire    pid_chk_ok; //  PID check
wire    [3:0] pid_field; //  PID field
reg     reject_rx_datpkt; //  Reject tx data packet enable
reg     reject_rx_dat_set; //  Reject rx data packet enable
reg     reject_tx_datpkt; //  Reject tx data packet enable
wire    reject_tx_dat_set; //  Reject rx data packet enable
//  Serial to parallel bit counter signals
reg     [2:0] ser2par_cnt; 
wire    [2:0] ser2par_cnt_d; 
wire    ser2par_cnt_en; //  Serial to parallel bit count enable
wire    ser2par_cnt_eq0; //  Serial to parallel bit count equals 0
wire    ser2par_cnt_eq1; //  Serial to parallel bit count equals 1
wire    ser2par_cnt_eq2; //  Serial to parallel bit count equals 2
wire    ser2par_cnt_eq6; //  Serial to parallel bit count equals 6
wire    ser2par_cnt_eq7; //  Serial to parallel bit count equals 7
wire    ser2par_cnt_ld; //  Serial to parallel bit count load
//  Serial to parallel register signals
reg     [23:0] ser2par_rg; 
wire    [23:0] ser2par_rg_d; 
wire    ser2par_rg_se; //  Ser2par reg shift enable
reg     sof_pid; //  SOF pid detect
// signal stall      : std_ulogic;  -- BDT stall control bit
reg     start_txd; //  Staring the tx data packet state machine
//  Token state machine state bits
reg     [3:0] tok_enum; //  Token state enumerated type
// signal tok_nstate      : tok_states; -- Next state bits
reg     [2:0] tok_pstate; //  Present state bits
reg     [2:0] tok_nstate; //  Next state bits
wire    token_done; //  Token processing done
wire    token_proc_en; //  Token processing enable
reg     tok_usboe; //  USBOE from token state maching
wire    [7:0] transmit_data; //  Transmit data
wire    transmit_done; //  Transmit done
wire    tgt_stall_set; //  A stall handshake has been sent by target
wire    [6:0] usb_addr; //  USB address
reg     usb_addr_eq; //  USB address equals
wire    usb_addr_eq_d; //  USB address equals data
wire    usb_bs_data; //  USB bit stuff data
wire    usb_crc_data; //  USB crc data
wire    usb_en; //  USB enable signal
wire    usb_rst_en_d; //  USB reset enable data
reg     usb_rst_en; //  USB reset enable
reg     usboe_early_r1; //  registers used to create pulse for early version of usboe
reg     usboe_early_r2; //  registers used to create pulse for early version of usboe
reg     usboe_early_r3; //  registers used to create pulse for early version of usboe
reg     usboe_early_r4; //  registers used to create pulse for early version of usboe
wire    usboe_nxt; //  USB output enable unregistered
reg     usboe_r; //  USB output enable data
reg     usboe_i; //  USB output enable internal
wire    valid_sof_pid_d; //  Valid SOF PID detect to hub
wire    valid_data_pid; //  Valid data PID
wire    valid_data_tgl; //  Valid data toggle bit
wire    valid_token_pid; //  Valid token PID
wire    valid_stall_pid; //  Valid token PID
wire    keep; //  BDT keep control bit
reg     resume_req_f; //  Resume signaling request delayed 1 ff
reg     resume_req_ff; //  Resume signaling request delayed 2 ffs
reg     lseop_en; //  LS EOP enable
wire    lseop_en_nxt; //  LS EOP enable 
wire    set_lseop_en; //  Set LS EOP enable
wire    clr_lseop_en; //  Clear LS EOP enable
wire    low_speed_signaling; //  Enable low speed signaling
//  host controller enable is used to enable the embedded host perations of the
//  core.   When IMPLEMENT_EMBEDED_HOST is '0' this signal causes the bulk of the
//  logic associated with the embedded host functions to be optimized out.

assign hc_en = IMPLEMENT_EMBEDED_HOST & host_mode_en; 
//  Assign debug bus
assign debug = {reject_rx_datpkt, det_eop, det_se0, det_sync, 
	ser2par_rg[0], tok_pstate, rxd_pstate, txd_pstate}; 
// ------------------------------------------------------------------------------
//  Dummy output signal assignments to remove unknowns from the simulations.   --
//  These assignments should be removed as the logic is implemented.           --
// ------------------------------------------------------------------------------
assign suspnd = 1'b 0; // 
//  Buffer USB outputs
assign dpo = idpo_d; 
assign dmo = VUSB_XCVR_MODE_SINGLE_ENDED == 1'b 1 ? ~(idpo_d | idmo_d) : 
	idmo_d; 
assign usboe = usboe_i; 
// ------------------------------------------------------------------------------
//  FIFO interfaces
// ------------------------------------------------------------------------------
//  Rx FIFO write data
//  This is the receive data that must be written into the Rx FIFO.
assign rx_wdata = {ser2par_rg[16], ser2par_rg[17], ser2par_rg[18], ser2par_rg[19], 
	ser2par_rg[20], ser2par_rg[21], ser2par_rg[22], ser2par_rg[23]}; 
//  Rx FIFO write enable
//  This signal when active high writes the receive data into the Rx FIFO.
assign rx_we = rx_fif_we; 
assign rx_fif_we = clk_en == 1'b 1 & own == 1'b 1 & 
	endpt_stall == 1'b 0 & rxd_pstate == RXD_BYTE2 & 
	ser2par_cnt_eq7 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
// ------------------------------------------------------------------------------
// 
//  Control/Data Bus In Definitions:
// 
//  Assign control inputs, do all in one spot for easy modifications
// 
//   cdb_in(43)  : hc_retry_disable - disable the automatic retry of host transfer
//                 failures.
assign hc_retry_disable = cdb_in[43]; 
//   cdb_in(42)  : resume_req - This signal causes the SIE to generate the resume
//                 signalling on the USB bus in device or embedded host mode. When
//                 operating in embedded host mode the resume signalling is 
//                 terminated with a LS EOP.
assign resume_req = cdb_in[42]; 
//   cdb_in(41)  : hc_rst_req - This signal causes the SIE to generate the reset
//                signalling on the USB bus in embedded host mode.
assign hc_rst_req = cdb_in[41]; 
//   cdb_in(40)     : txdsuspend_tokbusy dual use register output
//                     txd_suspend   - Transmit data packets are suspended on
//                                     the target until the uProcessor resets
//                                     the suspend ctl.
//                     hc_token_busy - The token statemachine has not completed
//                                     the last host token transaction.
assign txdsuspend_tokbusy = cdb_in[40]; 
//  cdb_in(39:32): hc_sof_thld - SOF threshold: count of USB byte times
//                    before the next SOF at which to discontinue Host
//                    transactions. 
assign hc_sof_thld = cdb_in[39:32]; 
//   cdb_in(31:28)  : usb_token_pid - This is the PID used in host mode token packets.
assign hc_token_pid = cdb_in[31:28]; 
//   cdb_in(27:24)  : usb_token_endpt - This is the Enpoint number  used in host mode
//                token packets. 
assign hc_token_endpt = cdb_in[27:24]; 
//   cdb_in(23:17)  : addr(6:0) - This is the USB address that the usb_sie
//                        will compare with token packets.
// 
assign usb_addr = cdb_in[23:17]; 
//   cdb_in(16)     : byte_count_eq - This bit informs the usb_sie that
//                        the DMA engine has reached a terminal byte count. 
//                        Data transmission should terminate when all remaining 
//                        data has been read from the Tx FIFO.
// 
assign byte_count_eq = cdb_in[16]; 
//   cdb_in(15)     : odd_rst - reset the PING/PONG odd bits.
// 
// odd_rst  <= cdb_in(15); -- clear BDT odd PING/PONG bits
//   cdb_in(14:8)    : ep_ctl - Endpoint control bits.
// 
//                 12           11         10         9         8
//           +------------+-----------+----------+----------+---------+
//           | ep_ctl_dis | ep_out_en | ep_in_en | ep_stall | ep_hshk |
//           +------------+-----------+----------+----------+---------+
// 
assign endpt_ctl_dis_d = cdb_in[12]; // 
assign endpt_out_en_d = cdb_in[11]; // 
assign endpt_in_en_d = cdb_in[10]; // 
assign endpt_stall = cdb_in[9]; // 
assign endpt_hshk_d = cdb_in[8]; // 
//   cdb_in(7:2)    : bdt(7:2) - These signals are the first byte of
//                        the BDT. They contain the following control bits:
// 
//                           7       6          5       4      3     2
//                        +-----+---------+----------+------+-----+------+
//                        | own | data0/1 |   keep   | ninc | dts | stall|
//                        +-----+---------+----------+------+-----+------+
// 
assign own_d = cdb_in[7]; //  BDT own control bit
assign data01 = cdb_in[6]; //  BDT data0/1 control bit
assign keep = cdb_in[5]; //  BDT keep control bit
// ninc        <= cdb_in(4); -- BDT ninc (no increment) control bit
assign dts = cdb_in[3]; //  BDT dts (data toggle sync) control bit
assign bdt_stall_d = cdb_in[2]; //  BDT stall control bit
//   cdb_in(1)      : bdt_valid - When this bit is active high it indicates
//                        that the BDT control bits are valid.
// 
assign bdt_valid = cdb_in[1]; 
//   cdb_in(0)      : usb_en - This is the USB enable signal from the control
//                        register.
// 
assign usb_en = cdb_in[0]; 
// ------------------------------------------------------------------------------
// 
//  Control/Data Bus Out Definitions:
// 
//   cdb_out(45)    : txd_token - the current token requires a tx data packet.
assign cdb_out[45] = txd_token; 
//   cdb_out(44)    : stall_set - Set signal for the stalled endpoint interrupt
assign cdb_out[44] = endpt_stall_clr; 
//   cdb_out(43)    : stall_set - Set signal for the stalled endpoint interrupt
assign cdb_out[43] = endpt_stall_set; 
//   cdb_out(42:41) : clear and set signals for the dual use register
//                     txd_suspend   - Transmit data packets are suspended on
//                                     the target until the uProcessor resets
//                                     the suspend ctl.
//                     hc_token_busy - The token statemachine has not completed
//                                     the last host token transaction.
assign cdb_out[42] = txdsuspend_tokbusy_clr; 
assign cdb_out[41] = txdsuspend_tokbusy_set; 
//   cdb_out(40)    : out_data01_pid - This bit is represents the DATA PID
//                    received during a SETUP or Rx Data Packet. If 0 we are
//                    receiving a DATA0 PID, if 1 we are receving a DATA1 
//                    PID. This value is written back to memory in the BDT
//                    control byte (bit 6).
// 
assign cdb_out[40] = out_data01_pid; 
//   cdb_out(39:36) : bdt_wrt_pid - These 4 bits represent the current
//                    token pid value. It is valid when a TOK_DNE is
//                    active.
// 
assign cdb_out[39:36] = bdt_wrt_pid; 
//   cdb_in(35:25)  : frame_num - These 11 bits represent the last frame 
//                    number that was received via a SOF packet. It is 
//                    valid after SOF_TOK has gone active.
// 
assign cdb_out[35:25] = frame_num; //  Current frame number
//   cdb_in(24:21)  : endpt - These four bits represent the current endpoint
//                    that the USB is using. This value will be stored by
//                    the up_int in the stat_rg when tok_dne_set=1.
// 
assign cdb_out[24:21] = current_endpt; //  Current end point
//   cdb_in(20)     : tx_datpkt_proc - This bit indicates that the usb_sie is
//                    processing a tx data packet.
// 
assign cdb_out[20] = tx_datpkt_proc; 
//   cdb_in(19)     : rx_datpkt_proc - This bit indicates that the usb_sie is
//                    processing a rx data packet.
// 
assign cdb_out[19] = rx_datpkt_proc; 
//   cdb_in(18:17)  : sie_dma_req - These two bits define the type of DMA
//                    request that the SIE is requesting. The bits are
//                    defined as:
// 
//                     17 16 | Type of DMA request
//                    -------+--------------------------------------
//                      0  1 | BDT read DMA request (i.e. 4 bytes)
//                      1  0 | BDT write DMA request (i.e. 4 bytes)
// 
//                    NOTE: The SIE will only activate one of the request
//                    bits at a time.
// 
assign cdb_out[18:17] = {(dma_wrt_bdt & own & ~endpt_stall & clk_en), 
	(dma_rd_bdt & clk_en)}; //  DMA read BDT (4 bytes) 
//  DMA write BDT (4 bytes) 
//   cdb_out(16)    : dma_early_req - This signal is used to have the DMA
//                    request the bus early. No bus cycles are performed
//                    with this request signal on the bus is requested.
//                    This is useful in design when the bus_gnt latency
//                    could exceed xxx ns, (zzz sie clks).
// 
assign cdb_out[16] = enable_early_req == 1'b 1 & current_token == PID_IN & 
	(tok_pstate == TOK_BYTE1 | tok_pstate == TOK_EOP) & 
	token_proc_en == 1'b 1 & usb_addr_eq == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//   cdb_out(15)     : bts_err_set - This signal when active will set the 
//                     BTS_ERR interrupt in the error status register
//                     (err_stat_rg).
// 
assign cdb_out[15] = bts_err_set; 
//   cdb_out(14)    : own_err_set - This signal when active will set the 
//                    OWN_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[14] = 1'b 0; 
//   cdb_out(13)    : dma_err_set - This signal when active will set the 
//                    DMA_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[13] = rx_fif_we & rx_full | tx_fif_re & tx_empty; //  or reading data that is not there
//   cdb_out(12)    : bto_err_set - This signal when active will set the 
//                    BTO_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[12] = bto_err_set; 
//  Bus timeout error interrupt set
assign bto_err_set = (rxd_pstate == RXD_IDLE | rxd_pstate == RXD_SYNC) & 
	mcek_cnt == 5'b 01110 ? 1'b 1 : 
	1'b 0; 
//  Turn around time for out/setup token or handshake
//   cdb_out(11)    : dfn8_err_set - This signal when active will set the 
//                    DF8N_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[11] = dfn8_err_tok | dfn8_err_rxd; //   from token or rx data
//   cdb_out(10)    : crc16_err_set - This signal when active will set the 
//                    CRC16_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign crc16_err_set = rxd_pstate == RXD_EOP & crc16_okay == 1'b 0 & 
	in_handshake_en == 1'b 0 & ser2par_cnt_eq0 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
assign cdb_out[10] = crc16_err_set; 
//   cdb_out(9)     : crc5_err_set - This signal when active will set the 
//                    CRC5_ERR interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[9] = hc_en == 1'b 0 ? crc5_err_set : 
	hc_sof_err_set; 
assign crc5_err_set = tok_pstate == TOK_EOP & crc5_okay == 1'b 0 & 
	ser2par_cnt_eq0 == 1'b 1 & hc_en == 1'b 0 ? 1'b 1 : 
	1'b 0; 
//   cdb_out(8)     : pid_err_set - This signal when active will set the 
//                    PID_ERr interrupt in the error status register
//                    (err_stat_rg).
// 
assign cdb_out[8] = (tok_pstate == TOK_PID & hc_en == 1'b 0 | 
	rxd_pstate == RXD_PID) & pid_chk_ok == 1'b 0 & 
	ser2par_cnt_eq7 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//   cdb_in(7)      : stall_int_set - for target a stall handshake has been
//                    sent. For host a stall handshake has been received. This
//                    signal will cause stall bit in the interrupt status
//                    register to be set. 
// 
assign cdb_out[7] = hc_en == 1'b 1 ? hc_stall_set : 
	tgt_stall_set; 
//   cdb_out(43)    : attach_set - This siganal when active will set the USB
//                    attach/detach interrupt in the interrupt status register.
assign cdb_out[6] = hc_attach_set; 
//   cdb_out(5)     : resume_set - This signal when active will set the 
//                    RESUME interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[5] = hc_resume_set; 
//   cdb_out(4)     : sleep_set - This signal when active will set the 
//                    SLEEP interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[4] = hc_en == 1'b 0 & jstate == 1'b 1 & 
	se0 == 1'b 0 & hc_sof_tc == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//   cdb_out(3)     : tok_dne_set - This signal when active will set the 
//                    TOK_DNE interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[3] = hc_en == 1'b 0 ? token_done : 
	hc_token_done & clk_en; 
//   cdb_out(2)     : sof_tok_set - This signal when active will set the 
//                    SOF_TOK interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[2] = frame_num_ld | hc_sof_thld_set; 
//   cdb_out(1)     : error_set - This signal when active will set the 
//                    ERROR interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[1] = 1'b 0; 
//   cdb_out(0)     : usb_rst_set - This signal when active will set the 
//                    USB_RST interrupt in the interrupt status register
//                    (istat_rg).
// 
assign cdb_out[0] = det_rst; //  Detect USB reset
//   clear and set signals for the dual use register txdsuspend_tokbusy
//                     txd_suspend   - Transmit data packets are suspended on
//                                     the target until the uProcessor resets
//                                     the suspend ctl.
//                     hc_token_busy - The token statemachine has not completed
//                                     the last host token transaction.
assign txdsuspend_tokbusy_set = hc_en == 1'b 0 ? txd_suspend_set : 
	1'b 0; 
assign txdsuspend_tokbusy_clr = hc_en == 1'b 1 ? hc_token_done : 
	1'b 0; 
assign txd_suspend = txdsuspend_tokbusy & ~hc_en; 
//  BDT own control bit load enable
//  The bdt own bit is sampled once during each transaction. It must be
//  valid by the time own_ld is active, or we will assume we do not own
//  the bdt and take the approriate action. Timing very important for in 
//  tokens not as critical for rx data packets.
assign own_ld = tx_datpkt_proc == 1'b 1 & txd_pstate == TXD_SYNC & 
	ser2par_cnt_eq6 == 1'b 1 | rxd_pstate == RXD_BYTE0 & 
	ser2par_cnt_eq6 == 1'b 1 | rxd_pstate == RXD_IDLE ? 1'b 1 : 
	1'b 0; 
//  for ISO packets that BTO
//  If the BDT Own bit is one and the BDT_STALL bit is one then set the endpoint
//  stall register.
assign endpt_stall_set = own_ld == 1'b 1 & own_d == 1'b 1 & 
	bdt_stall_d == 1'b 1 & txd_suspend == 1'b 0 & 
	current_token != PID_SETUP ? 1'b 1 : 
	1'b 0; 
//  If the last token caused us to fetch a valid owns bit and the current token
//  packet is the same as the last one the then the BDT loaded and it's owns bit
//  are still OK.  Other wise we will refetch the BDT.
assign own_ok = bdt_valid == 1'b 1 & own_d == 1'b 1 & 
	(own_ok_suspend == 1'b 0 | current_token != PID_IN) & 
	current_token_eq == 1'b 1 & current_endpt_eq == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Detect USB Reset
//  This signal looks for a USB reset condition. This is signified by a SE0 
//  for at least 2.5 us. The turn around timer is used to count a SE0 condition.
//  The usb_rst_en signal allows only a single interrupt to be generated during
//  the entire USB reset.
assign det_rst = mcek_cnt == 5'b 11111 & usb_rst_en == 1'b 1 & 
	det_se0 == 1'b 1 & se0_f == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Detect USB attach and detach
//  attach is detected when the the host is currently unattached, and a J-state
//  is observed for 2.5usec.  This interrupt should be disabled by the
//  processor when it enters the attached state.
assign hc_det_attach = hc_en == 1'b 1 & mcek_cnt == 5'b 11111 & 
	se0 == 1'b 0 & se0_f == 1'b 0 ? 1'b 1 : 
	1'b 0; 
//    an attach  generates an interrupt to the processor.
assign hc_attach_set = hc_det_attach; 
//  Detect USB resume / remote wake up event.
//  a resume is detected when the the host is currently suspended, and a K-state
//  is observed for 2.5usec.  This interrupt should be disabled by the
//  processor when it exits the suspend state.
assign hc_det_resume = mcek_cnt == 5'b 11111 & (se0 == 1'b 0 & 
	se0_f == 1'b 0 & (jstate == 1'b 0 & 
	jstate_f == 1'b 0)) ? 1'b 1 : 
	1'b 0; 
assign hc_resume_set = hc_det_resume; //    a resume generates an interrupt to the
//    processor. 
//  dettach is detected when the the host is currently attached, and a se0
//  is observed for 2.5usec that is not the result of a host reset request.
//  This looks the same to the SIE as a USB reset.  The processor will ferret out
//  the difference.
//  USB reset enable data
//  This signal is used to make sure that the USB reset logic will only
//  assert a single USB interrupt during a reset. Because the USB reset can 
//  be asserted for up to 10 ms we must only decode the USB reset on the first
//  2.5 us and not any of the remaining time. This will prevent multiple 
//  interrupts during the same USB reset.
assign usb_rst_en_d = mcek_cnt_clr == 1'b 1 ? 1'b 1 : 
	det_rst == 1'b 1 ? 1'b 0 : 
	usb_rst_en; //  No change
//  This signal decodes the end of packet condition.
//  se0 must have been active on the previous clock and this clock we
//  are in the "J" state.
assign det_eop = eop; 
// det_eop <= se0_f and rcv;
//  Detect single ended zero
assign det_se0 = se0; 
//  Detect SYNC
//  This signal looks at the last 9 bits of receive data. Looks for a
//  transition from idle followed by 01/h.
assign det_sync = (tok_pstate == TOK_SYNC | tok_pstate == TOK_PROC & 
	rxd_pstate == RXD_SYNC) & ser2par_rg[3:0] == 4'b 0001 ? 1'b 1 : 
	1'b 0; 
//  PID check
//  This logic performs the PID check.
assign pid_chk_ok = ser2par_rg[7:4] == ~ser2par_rg[3:0] ? 1'b 1 : 
	1'b 0; 
//  SOF pid
//  A valid SOF PID is decoded when the following conditions have been
//  satisfied:
//  1) current_token = "0101" This indicates a SOF PID
//  2) pid(3:0) = not pid(7:4) PID check field passes
assign valid_sof_pid_d = pid_chk_ok == 1'b 1 & pid_field == PID_SOF | 
	hc_en == 1'b 1 & hc_sof_req == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Valid token PID
//  A valid token PID is decoded when the following conditions have been
//  satisfied:
//  1) pid(1:0) = "01" This indicates a Token PID
//  2) pid(3:0) = not pid(7:4) PID check field passes
assign valid_token_pid = ser2par_rg[7:6] == 2'b 10 & pid_chk_ok == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Condition #2
//  Valid data PID
//  A valid data PID is decoded when the following conditions have been
//  satisfied:
//  NOTE: Should be able to but DTS code here!
//  1) pid(2:0) = "011" This indicates a Data PID
//  2) pid(3:0) = not pid(7:4) PID check field passes
assign valid_data_pid = (pid_field == PID_DATA0 | pid_field == PID_DATA1) & 
	pid_chk_ok == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Condition #2
//  Valid data toggle is true if the data toggle bit in the recieved packet
//  matches the expected data toggle bit from the BDT.
assign valid_data_tgl = dts == 1'b 0 | pid_field[3] == PID_DATA0[3] & 
	data01 == 1'b 0 | pid_field[3] == PID_DATA1[3] & 
	data01 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
assign valid_stall_pid = pid_field == PID_STALL & pid_chk_ok == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Condition #2
//  3) Endpoint enabled
//  4) CRC5 is okay
// valid_token <= '1' when (ser2par_rg(23 downto 22) = "10") and -- Condition #1
//                         (ser2par_rg(23 downto 20) = not(ser2par_rg(19 downto 16))) and
//                         -- Condition #2
//                         (endpt_en = '1') and   -- Condition #3
//                         (crc5_okay = '1') else -- Condition #4
//                '0';
//  Token processing done
//  Tell the token processing state machine that we are finished with 
//  IN and OUT data processing.
assign token_done = clk_en & own & ~endpt_stall & ~keep & 
	((tx_datpkt_done | rx_datpkt_done) & ~(reject_tx_datpkt | reject_rx_datpkt)); 
//  Tx Data Packet process
//  Enable the tx data packet state machine when the token process state machine
//  reaches TOK_PROC state and our current token is SETUP or OUT.
assign txd_token = hc_en == 1'b 0 & current_token == PID_IN | 
	hc_en == 1'b 1 & (current_token == PID_OUT | 
	current_token == PID_SETUP) ? 1'b 1 : 
	1'b 0; 
assign tx_datpkt_proc = tok_pstate == TOK_PROC & txd_token == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Rx Data Packet process
//  Enable the rx data packet state machine when the token process state machine
//  reaches TOK_PROC state and our current token is SETUP or OUT.
assign rx_datpkt_proc = tok_pstate == TOK_PROC & (hc_en == 1'b 1 & 
	current_token == PID_IN | hc_en == 1'b 0 & 
	(current_token == PID_OUT | current_token == PID_SETUP)) ? 1'b 1 : 
	1'b 0; 
//  Tx Data Packet process done
assign tx_datpkt_done = txd_pstate == TXD_DONE & rxd_pstate == RXD_WAIT ? 1'b 1 : 
	1'b 0; 
//  Rx Data Packet process done
assign rx_datpkt_done = rxd_pstate == RXD_DONE & txd_pstate == TXD_WAIT ? 1'b 1 : 
	1'b 0; 
//  Reject a host TX data packet if the it is nak'ed or you get a BTO
assign reject_tx_dat_set = in_handshake_en == 1'b 1 & (rxd_pstate == RXD_IDLE & 
	bto_err_set == 1'b 1 | rxd_pstate == RXD_PID & 
	ser2par_cnt_eq7 == 1'b 1 & (pid_chk_ok == 1'b 0 | 
	pid_field != PID_ACK & pid_field != PID_STALL)) ? 1'b 1 : 
	1'b 0; 
// send a stall interrupt if the recieve packet state machine gets a
//  stall handshake.
assign hc_stall_set = rxd_pstate == RXD_PID & ser2par_cnt_eq7 == 1'b 1 & 
	valid_stall_pid == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  USB bit stuff and crc data
//  The usb_sie can both transmit and reveive data. To reduce gate count
//  we reuse the bit stuff logic and crc16 logic. The bit stuff and crc16
//  logic only looks at the usb_bs_data signal. When we are transmitting data
//  the usb_bs_data signal is the output of the parallel to serial register.
//  If we are receiving data usb_bs_data is equal to the rcv signal.
assign usb_bs_data = txd_pstate != TXD_WAIT | hc_en == 1'b 1 & 
	tok_pstate != TOK_PROC ? usb_dout : 
	rcv; 
assign usb_crc_data = txd_pstate != TXD_WAIT | hc_en == 1'b 1 & 
	rxd_pstate == RXD_WAIT ? par2ser_rg[0] : 
	ser2par_rg[0]; 
// ------------------------------------------------------------------------------
//  Serial to Parallel Shift logic
// ------------------------------------------------------------------------------
//  Serial to parallel register shift enable
//  Always shift data except when detecting a bit stuffed '0'
//  Or when holding the SOF data until the crc and bit_stuff
//  errors have been checked.
assign ser2par_rg_se = zero_stuff == 1'b 1 | tok_pstate == TOK_EOP & 
	hc_en == 1'b 0 ? 1'b 0 : 
	1'b 1; 
//  Serial to parallel bit count enable
//  The serial to parallel count enable is active in when
//  ser2par_rg_se is active, but continues to shift during
//  the TOK_EOP state
assign ser2par_cnt_en = ~zero_stuff; 
// ------------------------------------------------------------------------------
//  NOTE: To conserve power might only shift portions of the shift register
//        at one time. For example in idle might only shift enough bit to detect
//        a sync, as the tok state machine process farther could enable more
//        of the shift register.
// ------------------------------------------------------------------------------
//  This code implements a shift register.
//  The ser2par_rg_d is the registered into ser2par_rg.
assign ser2par_rg_d = tok_pstate == TOK_IDLE ? {ser2par_rg[22:1], 1'b 1, rcv} : 
	ser2par_rg_se == 1'b 1 ? {ser2par_rg[22:0], rcv} : 
	ser2par_rg; //  No change
//  prepare for sync
//  when in idle
//  Shift in data
//  If shift enable true
//  Serial to parallel bit count load
//  The serial to parallel count load enable is active in reset and idle.
assign ser2par_cnt_ld = tok_pstate == TOK_IDLE | (tok_pstate == TOK_SYNC | 
	rxd_pstate == RXD_SYNC) & det_sync == 1'b 1 | 
	rxd_pstate == RXD_IDLE | start_txd == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//      (rxd_pstate = RXD_HSHK and txd_pstate = TXD_WAIT) or 
//  Implements serial to parallel bit counter
//  This counter is used to count the serial bits as they are shifted
//  into the serial to parallel register. If a stuffed bit '0' is dectected
//  (i.e. ser2par_rg_se = 0) this counter will hold while the '0' is removed
//  from the serial data stream.
assign ser2par_cnt_d = ser2par_cnt_ld == 1'b 1 ? 3'b 000 : 
	ser2par_cnt_en == 1'b 1 ? ser2par_cnt + 1 : 
	ser2par_cnt; //  No change
//  Load counter
//  Inc
//  Serial to parallel bit count equals 0
//  Must also include ser2par_cnt_en because it's possile that ser2par_cnt_eq0
//  could be active for two clocks if we get a bit-stuff when ser2par_cnt_eq0
//  is true. Adding the ser2par_cnt_en makes sure that this signal will only
//  be valid for one clock cycle.
assign ser2par_cnt_eq0 = ~ser2par_cnt[2] & ~ser2par_cnt[1] & ~ser2par_cnt[0] & ser2par_cnt_en; 
//  Serial to parallel bit count equals 1
//  Must also include ser2par_cnt_en because it's possile that ser2par_cnt_eq1
//  could be active for two clocks if we get a bit-stuff when ser2par_cnt_eq1
//  is true. Adding the ser2par_cnt_en makes sure that this signal will only
//  be valid for one clock cycle.
assign ser2par_cnt_eq1 = ~ser2par_cnt[2] & ~ser2par_cnt[1] & ser2par_cnt[0] & ser2par_cnt_en; 
//  Serial to parallel bit count equals 2
//  Must also include ser2par_cnt_en because it's possile that ser2par_cnt_eq2
//  could be active for two clocks if we get a bit-stuff when ser2par_cnt_eq2
//  is true. Adding the ser2par_cnt_en makes sure that this signal will only
//  be valid for one clock cycle.
assign ser2par_cnt_eq2 = ~ser2par_cnt[2] & ser2par_cnt[1] & ~ser2par_cnt[0] & ser2par_cnt_en; 
//  Serial to parallel bit count equals 6
//  Must also include ser2par_cnt_en because it's possile that ser2par_cnt_eq6
//  could be active for two clocks if we get a bit-stuff when ser2par_cnt_eq6
//  is true. Adding the ser2par_cnt_en makes sure that this signal will only
//  be valid for one clock cycle.
assign ser2par_cnt_eq6 = ser2par_cnt[2] & ser2par_cnt[1] & ~ser2par_cnt[0] & ser2par_cnt_en; 
//  Serial to parallel bit count equals 7
//  Must also include ser2par_cnt_en because it's possile that ser2par_cnt_eq7
//  could be active for two clocks if we get a bit-stuff when ser2par_cnt_eq7
//  is true. Adding the ser2par_cnt_en makes sure that this signal will only
//  be valid for one clock cycle.
assign ser2par_cnt_eq7 = ser2par_cnt[2] & ser2par_cnt[1] & ser2par_cnt[0] & ser2par_cnt_en; 
// ------------------------------------------------------------------------------
//  Parallel to Serial Shift logic
// ------------------------------------------------------------------------------
//  Parallel to serial register load enable
assign par2ser_rg_ld = hc_en == 1'b 1 & (tok_pstate == TOK_IDLE | 
	hc_ls_timing_set == 1'b 1 | ser2par_cnt_eq7 == 1'b 1 & 
	tok_pstate != TOK_PROC & tok_pstate != TOK_WAIT) | 
	txd_pstate == TXD_WAIT & tok_pstate == TOK_PROC | 
	ser2par_cnt_eq7 == 1'b 1 & (txd_pstate == TXD_SYNC | 
	txd_pstate == TXD_PID | txd_pstate == TXD_DATA | 
	txd_pstate == TXD_CRC16L | txd_pstate == TXD_PRE | 
	txd_pstate == TXD_LSDLY | txd_pstate == TXD_CRC16H) ? 1'b 1 : 
	1'b 0; 
//  Parallel to serial register shift enable
//  Always shift data except when detecting a bit stuffed '0'
assign par2ser_rg_se = zero_stuff == 1'b 1 | txd_pstate == TXD_DELAY ? 1'b 0 : 
	1'b 1; 
//  Do not shift in this state
//  This code implements a the parallel to serial shift register.
//  Data to be transmitted is loaded in this register then shifted out serially.
assign par2ser_rg_d = par2ser_rg_ld == 1'b 1 ? transmit_data : 
	par2ser_rg_se == 1'b 1 ? {1'b 0, par2ser_rg[7:1]} : 
	par2ser_rg; //  No change
//  Load data
//  when load enable true
//  Shift out data
//  when shift enable true
//  set an interrupt if a STALL handshake has been sent.
assign tgt_stall_set = txd_pstate == TXD_PID ? endpt_stall : 
	1'b 0; 
//  Tx Data Packet pid data
always @(hc_en or tok_pstate or hc_sof_req or low_speed_req or hc_ls_timing
 or rxd_pstate or endpt_stall or own or data01 or endpt_hshk
 or current_token or rx_overrun_nak or txd_pstate or hc_token_pid)
   begin : txd_pid_data_proc
   if (hc_en == 1'b 1 & tok_pstate == TOK_SYNC & 
	hc_sof_req == 1'b 1)
      begin
      txd_pid_data <= PID_SOF;	//  host SOF transmit packet
      end
   else if (hc_en == 1'b 1 & (tok_pstate == TOK_SYNC | 
	txd_pstate == TXD_SYNC) & low_speed_req == 1'b 1 & 
	hc_ls_timing == 1'b 0 )
      begin
      txd_pid_data <= PID_PRE;	//  host PRE_PID prefix to low speed dev
      end
   else if (hc_en == 1'b 1 & tok_pstate == TOK_SYNC & 
	hc_sof_req == 1'b 0 )
      begin
      txd_pid_data <= hc_token_pid;	//  host token packet
      end
   else if (rxd_pstate == RXD_WAIT & endpt_stall == 1'b 0 & 
	(own == 1'b 1 & data01 == 1'b 0 | 
	endpt_hshk == 1'b 0) )
      begin
      txd_pid_data <= PID_DATA0;	
      end
//  DATA0
//  ISO endpoints use DATA0
   else if (rxd_pstate == RXD_WAIT & endpt_stall == 1'b 0 & 
	own == 1'b 1 & data01 == 1'b 1 )
      begin
      txd_pid_data <= PID_DATA1;	
      end
//  DATA1
   else if (endpt_stall == 1'b 1 & current_token != PID_SETUP )
      begin
      txd_pid_data <= PID_STALL;	//  STALL
      end
   else if (own == 1'b 0 | rx_overrun_nak == 1'b 1 )
      begin
      txd_pid_data <= PID_NAK;	//  NAK
      end
   else if (own == 1'b 1 )
      begin
      txd_pid_data <= PID_ACK;	//  ACK
//     txd_pid_data <= "XXXX";
      end
   else
      begin
      txd_pid_data <= 4'b 0000;	
      end
   end
//  Transmit done
//  We are done transmiting when the DMA engine byte count has reached 0 and
//  the Tx FIFO is empty and contains no valid data.
assign transmit_done = byte_count_eq == 1'b 1 & tx_empty == 1'b 1 & 
	tx_valid == 1'b 0 ? 1'b 1 : 
	1'b 0; 
//  Transmit host data
assign hc_tx_data = hc_sof_req == 1'b 1 ? frame_num : 
	{hc_token_endpt, usb_addr}; 
assign hc_txd_byte = tok_pstate == TOK_PID ? hc_tx_data[7:0] : 
	{hc_tx_data[7:3], hc_tx_data[10:8]}; 
//  Transmit data
assign transmit_data = zero_stuff_inhibit == 1'b 1 | force_bit_stuff_err == 1'b 1 ? 8'b 11111111 : 
	hc_ls_timing_set == 1'b 1 ? 8'b 10000000 : 
	txd_pstate == TXD_SYNC | tok_pstate == TOK_SYNC & 
	hc_en == 1'b 1 ? {~txd_pid_data, txd_pid_data} : 
	hc_en == 1'b 1 & (tok_pstate == TOK_PID | 
	tok_pstate == TOK_BYTE0) ? hc_txd_byte : 
	txd_pstate == TXD_PID | txd_pstate == TXD_DATA ? tx_rdata : 
	8'b 10000000; //  Sync byte
// force_bit_stuff_error
//  Sync byte for low speed
//  Tx FIFO read enable
assign tx_re = tx_fif_re; 
assign tx_fif_re = clk_en == 1'b 1 & ser2par_cnt_eq7 == 1'b 1 & 
	(txd_pstate == TXD_PID | txd_pstate == TXD_DATA) & 
	transmit_done == 1'b 0 & own == 1'b 1 & 
	endpt_stall == 1'b 0 & out_handshake_en == 1'b 0 ? 1'b 1 : 
	1'b 0; 
//  On FIFO underrun force a bit stuff error.
assign force_bit_stuff_err = tx_fif_re & tx_empty; 
//  FIFO flush enable
assign flush = det_rst | dma_rd_bdt; //  clear the rx and tx FIFOs when loading a new
//  DMA descriptor
//  USB address equals
//  Must make sure that the address within the token equals our current address.
// usb_addr_eq <= '1' when usb_addr = ser2par_rg(16 downto 10) else '0';
assign usb_addr_eq_d = usb_addr == {ser2par_rg[4], ser2par_rg[5], ser2par_rg[6], 
	ser2par_rg[7], ser2par_rg[8], ser2par_rg[9], ser2par_rg[10]} ? 1'b 1 : 
	1'b 0; 
//  Token processing enable
assign token_proc_en = endpt_out_en == 1'b 1 & endpt_in_en == 1'b 1 & 
	endpt_hshk == 1'b 1 & endpt_ctl_dis == 1'b 0 & 
	current_token == PID_SETUP | endpt_out_en == 1'b 1 & 
	current_token == PID_OUT | endpt_in_en == 1'b 1 & 
	current_token == PID_IN ? 1'b 1 : 
	1'b 0; 
//  SETUP TOKENS (control endpoints must enable in and out and handshake)
//  RX DATA PACKETS
//  TX DATA PACKETS
//  In handshake enable
assign in_handshake_en = txd_pstate == TXD_HSHK ? 1'b 1 : 
	1'b 0; 
//  Out handshake enable
assign out_handshake_en = rxd_pstate == RXD_HSHK ? 1'b 1 : 
	1'b 0; 
//  Load current token register
assign current_token_ld = tok_pstate == TOK_PID & ser2par_cnt_eq7 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Load current endpoint register
//   '1' when (tok_pstate = TOK_BYTE1) and ser2par_cnt_eq7 = '1' else '0'; 
assign current_endpt_ld = tok_pstate == TOK_BYTE1 & ser2par_cnt_eq2 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  Last bit stuff enable
assign last_bit_stuff_en = usb_bs_data == 1'b 1 & one_bit_cnt == 3'b 101 & 
	ser2par_cnt_eq7 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
// ------------------------------------------------------------------------------
//  Bit stuff logic
// 
//  This logic will count the number of 1's received. When this count reaches
//  6 the next bit should be a '0'. If so this bit should be removed from the
//  receive data stream. If the next bit is not a '0' then a bit stuff error
//  has occurred.
// ------------------------------------------------------------------------------
//  One bit count load enable
//  Reset this counter whenever we are in reset state or we detect a
//  received '0' bit, otherwise it will always count. If this counter
//  ever reaches 7 and we are not in ILDE then a bit stuff error has occured.
assign one_bit_cnt_ld = tok_pstate == TOK_IDLE | tok_pstate == TOK_EOP | 
	rxd_pstate == RXD_IDLE | rxd_pstate == RXD_EOP | 
	rxd_pstate == RXD_HSHK | zero_stuff == 1'b 1 | 
	usb_bs_data == 1'b 0 | se0 == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  the packet ended.
assign zero_stuff = one_bit_cnt == 3'b 110 & zero_stuff_inhibit == 1'b 0 ? 1'b 1 : 
	1'b 0; 
assign one_bit_cnt_d = one_bit_cnt_ld == 1'b 1 ? 3'b 000 : 
	one_bit_cnt + 1; //  Inc
//  Load start count
assign bts_err_set = (hc_en == 1'b 0 & (tok_pstate == TOK_PID | 
	tok_pstate == TOK_BYTE0 | tok_pstate == TOK_BYTE1 | 
	tok_pstate == TOK_EOP) | rxd_pstate == RXD_SYNC | 
	rxd_pstate == RXD_PID | rxd_pstate == RXD_BYTE0 | 
	rxd_pstate == RXD_BYTE1 | rxd_pstate == RXD_BYTE2 | 
	rxd_pstate == RXD_EOP) & zero_stuff == 1'b 1 & 
	(rcv == 1'b 1 | se0 == 1'b 1) & 
	clk_en == 1'b 1 ? 1'b 1 : 
	1'b 0; 
assign dma_rd_bdt = dev_dma_rd_bdt | hc_dma_rd_bdt; 
// ------------------------------------------------------------------------------
// 
//      Process: rx_srst_regs -- Receive registers
// 
//   Parameters: clk     -- Clock
// 
//  Description: This process implements the USB SIE receive registers
//   and synchronization flip flops with syncronous resets.
// 
// ------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : rx_srst_regs
   if (rst_a == 1'b 1)
      begin
      tok_pstate <= TOK_IDLE;	//  Goto to reset state
      txd_pstate <= TXD_WAIT;	//  Goto to wait state
      rxd_pstate <= RXD_WAIT;	//  Goto to wait state
      rx_overrun_nak <= 1'b 0;	//  Clear FIFO overrun error
      mcek_cnt <= 5'b 00000;	
      own <= 1'b 0;	
      own_ok_suspend <= 1'b 0;	
      bit_stuff_err <= 1'b 0;	
      dma_re_rd_bdt <= 1'b 0;	
      frame_num <= {3'b 000, 8'b 00000000};	
      lseop_en <= 1'b 0;	
      sof_cnt_clr0 <= 1'b 0;	
      sof_cnt_clra <= 1'b 0;	
      sof_pid <= 1'b 0;	
      zero_stuff_inhibit <= 1'b 0;	
      usb_rst_en <= 1'b 1;	
      out_data01_pid <= 1'b 0;	
      crc16_data <= {16{1'b 1}};	
      if (lsdev == 1)
         begin
         idpo <= 1'b 0;	
         end
      else
         begin
         idpo <= 1'b 1;	
         end
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         tok_pstate <= TOK_IDLE;	//  Goto to reset state
         txd_pstate <= TXD_WAIT;	//  Goto to wait state
         rxd_pstate <= RXD_WAIT;	//  Goto to wait state
         rx_overrun_nak <= 1'b 0;	//  Clear FIFO overrun error
         mcek_cnt <= 5'b 00000;	
         own <= 1'b 0;	
         own_ok_suspend <= 1'b 0;	
         bit_stuff_err <= 1'b 0;	
         dma_re_rd_bdt <= 1'b 0;	
         frame_num <= {3'b 000, 8'b 00000000};	
         lseop_en <= 1'b 0;	
         sof_cnt_clr0 <= 1'b 0;	
         sof_cnt_clra <= 1'b 0;	
         sof_pid <= 1'b 0;	
         zero_stuff_inhibit <= 1'b 0;	
         usb_rst_en <= 1'b 1;	
         out_data01_pid <= 1'b 0;	
         crc16_data <= {16{1'b 1}};	
         if (lsdev == 1)
            begin
            idpo <= 1'b 0;	
            end
         else
            begin
            idpo <= 1'b 1;	
            end
         end
      else
         begin
         if (clk_en == 1'b 1)
            begin
            if (det_rst == 1'b 1 | hc_reset == 1'b 1)
               begin
               tok_pstate <= TOK_IDLE;	//  Goto to reset state
               end
//  If reset active
            else
               begin
               tok_pstate <= tok_nstate;	//  Else update pstate
//  Register tx data packet state machine state bits
               end
            if (det_rst == 1'b 1 | hc_reset == 1'b 1)
               begin
               txd_pstate <= TXD_WAIT;	//  Goto to wait state
               end
//  If reset active
            else
               begin
               txd_pstate <= txd_nstate;	//  Else update pstate
//  Register rx data packet state machine state bits
               end
            if (det_rst == 1'b 1 | hc_reset == 1'b 1)
               begin
               rxd_pstate <= RXD_WAIT;	//  Goto to wait state
               end
//  If reset active
            else
               begin
               rxd_pstate <= rxd_nstate;	//  Else update pstate
//  Register the Rx data overrun errors so that a NAK may be generated.
               end
            if (txd_pstate == TXD_EOP | tok_pstate == TOK_IDLE)
               begin
               rx_overrun_nak <= 1'b 0;	//  clear when a packet is sent
               end
            else if (rx_fif_we == 1'b 1 & rx_full == 1'b 1 & 
	endpt_hshk == 1'b 1 )
               begin
               rx_overrun_nak <= 1'b 1;	
//  SIE counter
//  This counter times 3 different events
//   1) USB reset:  SE0 is asserted for 2.5 us.
//   2) USB attach: SE0 is false and rcv doesn't move for 2.5 us
//   3) USB Buss Time Out (BTO) if the bus is idle for 2.5 us when expecting rcv
//      data or acknoledge.
//   4) USB LS EOP: When in host controller mode this counter is used to 
//      generate a LS EOP to terminate resume signaling.
//  In any of these cases the counter is enabled when there are no transitions
//  and is cleared on a transition.
               end
//  if not an ISO endpoint
            if (mcek_cnt_clr == 1'b 1)
               begin
               mcek_cnt <= 5'b 00000;	
               end
            else
               begin
               mcek_cnt <= mcek_cnt + 1'b 1;	
//  Develope 2 cycle wide sof_clr pulse to send to the clken_12 domain
               end
            sof_cnt_clr0 <= mcek_cnt_clr;	
            sof_cnt_clra <= mcek_cnt_clr | sof_cnt_clr0;	
//  BDT own control bit
//  The bdt own bit is sampled once during each transaction. It must be
//  valid by the time own_ld is active, or we will assume we do not own
//  the bdt and take the approriate action.
            if (own_ld == 1'b 1)
               begin
               if (txd_suspend == 1'b 1 & endpt_hshk == 1'b 1)
                  begin
                  own <= 1'b 0;	
                  end
               else
                  begin
                  own <= own_d;	
                  end
               end
//  if txd is suspended respond to any non ISO token as if the interface is not
//  ready. 
//  Suspend the BDT caching operation when txd_suspend is asserted, and make
//  sure that a new BDT is read before allowing it to be cached.
            if (txd_suspend == 1'b 1)
               begin
               own_ok_suspend <= 1'b 1;	
               end
            else if (dma_rd_bdt == 1'b 1 )
               begin
               own_ok_suspend <= 1'b 0;	
//  bit stuff error in this packet
               end
            if (tok_pstate == TOK_SYNC | rxd_pstate == RXD_SYNC)
               begin
               bit_stuff_err <= 1'b 0;	
               end
            else if (bts_err_set == 1'b 1 )
               begin
               bit_stuff_err <= 1'b 1;	
//   DMA BDT re-read request - set when there is an error in the data packet
//   transmition to force a the DMA registers to be reloaded.
               end
//  set on error detection.
            if (dma_rd_bdt == 1'b 1)
               begin
               dma_re_rd_bdt <= 1'b 0;	
               end
            else if (reject_rx_dat_set == 1'b 1 | reject_tx_dat_set == 1'b 1 )
               begin
               dma_re_rd_bdt <= 1'b 1;	
//  Current frame number register 
               end
            frame_num <= frame_num_d;	
//   DMA BDT re-read request - set when there is an error in the data packet
            lseop_en <= lseop_en_nxt;	
//  register that the current token is an SOF token
//  SOF tokens are NOT stored in the current_token register, because it messes
//  up the owns_ok signal used for BDT caching.
            if (current_token_ld == 1'b 1)
               begin
               sof_pid <= valid_sof_pid_d;	
//  Bit stuff disable for packet cancelation.
               end
            if (txd_pstate == TXD_EOP)
               begin
               zero_stuff_inhibit <= 1'b 0;	//  been stuffed
               end
//  clear after a bit should have
            else if (force_bit_stuff_err == 1'b 1 )
               begin
               zero_stuff_inhibit <= 1'b 1;	
               end
//  set when error is forced
            usb_rst_en <= usb_rst_en_d;	
//  Out data01 pid register 
            out_data01_pid <= out_data01_pid_d;	
//  Implements CRC16 register
            if (crc16_data_ld == 1'b 1)
               begin
               crc16_data <= nxt_crc16_data;	//  Update crc data
               end
            else
               begin
               crc16_data <= crc16_data;	//  No change
//  Register USB outputs
               end
            idpo <= idpo_d;	
            end
//  Register token state machine state bits
//  clk_en
         end
//  srst  --vsync_rst
      end
//  clk'event and (clk = '1')
   end
// -----------------------------------------------
//  Set LS EOP enable
assign set_lseop_en = ~resume_req_f & resume_req_ff; 
assign lseop_en_nxt = clr_lseop_en == 1'b 1 ? 1'b 0 : 
	set_lseop_en == 1'b 1 ? 1'b 1 : 
	lseop_en; 
//  Clear LS EOP enable
assign clr_lseop_en = hc_en == 1'b 0 | resume_req == 1'b 1 | 
	lseop_en == 1'b 1 & mcek_cnt == 5'b 01111 ? 1'b 1 : 
	1'b 0; 
// ------------------------------------------------------------------------------
// 
//      Process: rx_regs -- Receive registers
// 
//   Parameters: clk     -- Clock
// 
//  Description: This process implements the USB SIE receive registers
//   and synchronization flip flops.
// 
// ------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : rx_regs
   if (rst_a == 1'b 1)
      begin
      resume_req_ff <= 1'b 0;	
      resume_req_f <= 1'b 0;	
      reject_rx_datpkt <= 1'b 0;	
      reject_tx_datpkt <= 1'b 0;	
      se0_f <= 1'b 0;	
      jstate_f <= 1'b 0;	
      endpt_ctl_dis <= 1'b 0;	
      endpt_in_en <= 1'b 0;	
      endpt_out_en <= 1'b 0;	
      endpt_hshk <= 1'b 0;	
      ser2par_rg <= {24{1'b 0}};	
      par2ser_rg <= {8{1'b 0}};	
      ser2par_cnt <= {3{1'b 0}};	
      one_bit_cnt <= {3{1'b 0}};	
      current_token <= {4{1'b 0}};	
      current_token_eq <= 1'b 0;	
      current_endpt <= {4{1'b 0}};	
      current_endpt_eq <= 1'b 0;	
      usb_addr_eq <= 1'b 0;	
      usboe_i <= 1'b 0;	
      usboe_r <= 1'b 0;	
      crc5_data <= {5{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         resume_req_ff <= 1'b 0;	
         resume_req_f <= 1'b 0;	
         reject_rx_datpkt <= 1'b 0;	
         reject_tx_datpkt <= 1'b 0;	
         se0_f <= 1'b 0;	
         jstate_f <= 1'b 0;	
         endpt_ctl_dis <= 1'b 0;	
         endpt_in_en <= 1'b 0;	
         endpt_out_en <= 1'b 0;	
         endpt_hshk <= 1'b 0;	
         ser2par_rg <= {24{1'b 0}};	
         par2ser_rg <= {8{1'b 0}};	
         ser2par_cnt <= {3{1'b 0}};	
         one_bit_cnt <= {3{1'b 0}};	
         current_token <= {4{1'b 0}};	
         current_token_eq <= 1'b 0;	
         current_endpt <= {4{1'b 0}};	
         current_endpt_eq <= 1'b 0;	
         usb_addr_eq <= 1'b 0;	
         usboe_i <= 1'b 0;	
         usboe_r <= 1'b 0;	
         crc5_data <= {5{1'b 0}};	
         end
      else
         begin
         if (clk_en == 1'b 1)
            begin
            resume_req_ff <= resume_req_f;	
            resume_req_f <= resume_req;	
//  Register the Rx and Tx packet reject signals
            if (tok_pstate == TOK_IDLE)
               begin
               reject_rx_datpkt <= 1'b 0;	
               end
            else if (reject_rx_dat_set == 1'b 1 )
               begin
               reject_rx_datpkt <= 1'b 1;	
               end
            if (tok_pstate == TOK_IDLE)
               begin
               reject_tx_datpkt <= 1'b 0;	
               end
            else if (reject_tx_dat_set == 1'b 1 )
               begin
               reject_tx_datpkt <= 1'b 1;	
               end
            se0_f <= se0;	//  registered copies for transition
            jstate_f <= jstate;	//  detection. 
//  Endpoint tx data packet enabled (Input endpoint)
            endpt_ctl_dis <= endpt_ctl_dis_d;	
//  Endpoint tx data packet enabled (Input endpoint)
            endpt_in_en <= endpt_in_en_d;	
//  Endpoint rx direction
            endpt_out_en <= endpt_out_en_d;	
//  Endpoint enabled
            endpt_hshk <= endpt_hshk_d;	
//  Serial to parallel shift register
            ser2par_rg <= ser2par_rg_d;	
//  Parallel to serial register 
            par2ser_rg <= par2ser_rg_d;	
//  Implements serial to parallel bit counter
            ser2par_cnt <= ser2par_cnt_d;	
//  One bit count register
            one_bit_cnt <= one_bit_cnt_d;	
//  Current token register
            current_token <= current_token_d;	
//  Current_token comparitor
            if (current_token_ld == 1'b 1)
               begin
               if (current_token == current_token_d)
                  begin
                  current_token_eq <= 1'b 1;	
                  end
               else
                  begin
                  current_token_eq <= 1'b 0;	
                  end
               end
//  Current endpoint register 
            current_endpt <= current_endpt_d;	
//  Current_token comparitor
            if (current_endpt_ld == 1'b 1)
               begin
               if (current_endpt == current_endpt_d)
                  begin
                  current_endpt_eq <= 1'b 1;	
                  end
               else
                  begin
                  current_endpt_eq <= 1'b 0;	
                  end
               end
//  USB address equals 
            if (current_endpt_ld == 1'b 1)
               begin
               usb_addr_eq <= usb_addr_eq_d;	
               end
            else
               begin
               usb_addr_eq <= usb_addr_eq;	
//  Register USB output enable 
               end
            usboe_i <= usboe_r | usboe_nxt;	//  assert the OE for one idle clock 
            usboe_r <= usboe_nxt;	//  after EOP or reset_request.
//  Implements CRC5 register
            if (crc5_data_ld == 1'b 1)
               begin
               crc5_data <= nxt_crc5_data;	//  Update crc data
               end
            else
               begin
               crc5_data <= crc5_data;	//  No change
               end
            end
//  Pulse generator for resume signaling
         end
      end
   end
// -----------------------------------------------
// ------------------------------------------------------------------------------
// 
//      Process: usboe_early_proc
// 
//   Parameters: clk     -- Clock
// 
//  Description: This process generates the pulse for the early version of usboe
//               Once the early signal is triggered, it is held for four clk_en
//               cycles, which will give it enough time for generating an early
//               OE signal in the ratematch, after that, the regular usboe signal
//               will have propagated through.
// 
// ------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : usboe_early_proc
   if (rst_a == 1'b 1)
      begin
      usboe_early_r1 <= 1'b 0;	
      usboe_early_r2 <= 1'b 0;	
      usboe_early_r3 <= 1'b 0;	
      usboe_early_r4 <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usboe_early_r1 <= 1'b 0;	
         usboe_early_r2 <= 1'b 0;	
         usboe_early_r3 <= 1'b 0;	
         usboe_early_r4 <= 1'b 0;	
         end
      else
         begin
         if (clk_en == 1'b 1)
            begin
            if (rxd_nstate == RXD_HSHK & rxd_pstate != RXD_HSHK | 
	tok_nstate == TOK_PROC & tok_pstate != TOK_PROC & 
	txd_token == 1'b 1 | tok_usboe == 1'b 1 & 
	tok_pstate == TOK_IDLE)
               begin
               usboe_early_r1 <= 1'b 1;	
               end
            else
               begin
               usboe_early_r1 <= 1'b 0;	
               end
            usboe_early_r2 <= usboe_early_r1;	
            usboe_early_r3 <= usboe_early_r2;	
            usboe_early_r4 <= usboe_early_r3;	
            end
//  use an edge detect on state changing to generate a pulse for usboe_early
//  then hold that pulse through four clk_en cycles
         end
      end
   end
// -----------------------------------------------
assign usboe_early = usboe_early_r1 | usboe_early_r2 | usboe_early_r3 | usboe_early_r4; 
//  EMBEDDED HOST REMOVE ON                       
// ------------------------------------------------------------------------------
// 
//      Process: host_regs -- registers used by the embedded host controller.
// 
//   Parameters: clk     -- Clock
// 
//  Description: These processies implement the USB SIE host mode registers
//               The sof_regs process contains the host frame timer which runs
//               off a constant 12MHz clock or clock enable.
//               The host_regs  processor implements the registers that change
//               state based on the dpll output clock or clock enable.
// 
// ------------------------------------------------------------------------------
//  gate the host register outputs with the implement embedded host
//  configuration constant, so that registers will be removed during
//  logic optimization if host mode is not enabled.
// ------------------------------------------------------------------------------
assign hc_dma_rd_bdt = hc_dma_rd_bdt_q & hc_en; 
assign hc_ls_timing = hc_ls_timing_q & hc_en; 
assign hc_sof_req = hc_sof_req_q & hc_en; 
assign hc_sof_req_f = hc_sof_req_fq & hc_en; 
assign hc_token_busy_f = hc_token_busy_fq & hc_en; 
assign hc_token_inhibit_d = hc_token_inhibit_dq & hc_en; 
assign hc_token_inhibit = hc_token_inhibit_q & hc_en; 
assign hc_token_inhibit_f = hc_token_inhibit_fq & hc_en; 
assign hc_sof_req_set = hc_sof_req_set_q & hc_en; 
assign hc_en_f = hc_en_fq; 
assign hc_rxd_pid = hc_rxd_pid_q; 
always @(posedge clk or posedge rst_a)
   begin : host_regs
   if (rst_a == 1'b 1)
      begin
      hc_dma_rd_bdt_q <= 1'b 0;	
      hc_ls_timing_q <= 1'b 0;	
      hc_token_busy_fq <= 1'b 0;	
      hc_sof_req_q <= 1'b 0;	
      hc_sof_req_fq <= 1'b 0;	
      hc_token_inhibit_q <= 1'b 0;	
      hc_token_inhibit_fq <= 1'b 0;	
      hc_sof_req_set_q <= 1'b 0;	
      hc_en_fq <= 1'b 0;	
      hc_rxd_pid_q <= 4'b 0000;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_dma_rd_bdt_q <= 1'b 0;	
         hc_ls_timing_q <= 1'b 0;	
         hc_token_busy_fq <= 1'b 0;	
         hc_sof_req_q <= 1'b 0;	
         hc_sof_req_fq <= 1'b 0;	
         hc_token_inhibit_q <= 1'b 0;	
         hc_token_inhibit_fq <= 1'b 0;	
         hc_sof_req_set_q <= 1'b 0;	
         hc_en_fq <= 1'b 0;	
         hc_rxd_pid_q <= 4'b 0000;	
         end
      else
         begin
         if (clk_en == 1'b 1)
            begin
            if (det_rst == 1'b 1 | hc_en == 1'b 0 | 
	usb_en == 1'b 0 | tok_pstate == TOK_EOP & 
	ser2par_cnt_eq1 == 1'b 1)
               begin
               hc_sof_req_q <= 1'b 0;	
               end
//  EOP of the SOF packet is sent
            else if (hc_sof_req_set == 1'b 1 )
               begin
               hc_sof_req_q <= 1'b 1;	
               end
//   
            hc_sof_req_fq <= hc_sof_req;	//  one clock delayed
//  hc_ls_timing Host Low Speed Timing is a state bit used to generate low
//  speed packets for low speed devices.  Host Low Speed Timing is entered
//  after the PRE_PID prefix is sent and is exited at the end of the 
//  transaction.
            if (hc_en == 1'b 0 | host_wo_hub == 1'b 1)
               begin
               hc_ls_timing_q <= low_speed_req;	//  for devices or directly connected
//  devices allow software to control the speed directly.
               end
            else if (hc_ls_timing_clr == 1'b 1 )
               begin
               hc_ls_timing_q <= 1'b 0;	//  reset the low speed timing state between packets
               end
            else if (hc_ls_timing_set == 1'b 1 )
               begin
               hc_ls_timing_q <= 1'b 1;	//  enter the low speed timing state after the 
//  SOF warning, token send inhibit
               end
//  PRE_PID prefix has been sent.
            if (det_rst == 1'b 1 | hc_en == 1'b 0 | 
	tok_pstate == TOK_EOP & hc_sof_req == 1'b 1)
               begin
               hc_token_inhibit_q <= 1'b 0;	//  when then EOP of the SOF packet is sent
               end
//  reset the Inhibit
            else if (hc_token_inhibit_d == 1'b 1 )
               begin
               hc_token_inhibit_q <= 1'b 1;	//  inhibit host transactions until when the SOF counter 
               end
//  reaches the warning theshold
            hc_token_inhibit_fq <= hc_token_inhibit;	//  one clock delayed.
//  Register the host dma read request
            hc_dma_rd_bdt_q <= hc_en & (hc_token_req | (tx_datpkt_done & reject_tx_datpkt | 
	rx_datpkt_done & reject_rx_datpkt));	
//  reset token dma bdt on unsuccessfull transactions 
//  Register the hc_token_busy signal for rising edge detection.
            hc_token_busy_fq <= hc_token_busy;	
//  SOF token packet request request a SOF packet when the SOF 
//  counter reaches zero.
            hc_sof_req_set_q <= ~det_rst & hc_en & usb_en & hc_sof_tc;	
            hc_en_fq <= hc_en;	//  register host mode for edge
//  detection. 
            if (rxd_pstate == RXD_PID & ser2par_cnt_eq7 == 1'b 1)
               begin
               hc_rxd_pid_q <= pid_field;	//  record the received pid
               end
            else if (bto_err_set == 1'b 1 )
               begin
               hc_rxd_pid_q <= 4'b 0000;	//  use 0x0 for BTO notification
               end
            else if (crc16_err_set == 1'b 1 | dfn8_err_rxd == 1'b 1 | 
	bit_stuff_err == 1'b 1 )
               begin
               hc_rxd_pid_q <= 4'b 1111;	//  use 0xf for data error
               end
//  bit stuff, write 0xf to the BDT PID
            end
//  SOF token packet request
//  clk_en = '1'
         end
//  srst
      end
//  clk'event and (clk = '1')
   end
// -----------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : hc_token_inhibit_dq_PROC
   if (rst_a == 1'b 1)
      begin
      hc_token_inhibit_dq <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_token_inhibit_dq <= 1'b 0;	
         end
//  synchronous resets
      else if (clken_12 == 1'b 1 )
         begin
         if (det_rst == 1'b 1 | hc_en == 1'b 0)
            begin
            hc_token_inhibit_dq <= 1'b 0;	
            end
         else if (hc_sof_cnt[15:11] == 5'b 00000 & hc_sof_cnt[10:3] == hc_sof_thld )
            begin
            hc_token_inhibit_dq <= 1'b 1;	
            end
         else if (hc_token_inhibit == 1'b 1 )
            begin
            hc_token_inhibit_dq <= 1'b 0;	
            end
         end
      end
//  clk_sof'event and (clk_sof = '1') then
   end

assign hc_token_req = hc_token_busy & ~hc_token_busy_f; 
assign hc_token_busy = txdsuspend_tokbusy & hc_en; 
assign hc_reset = hc_en ^ hc_en_f; //  reset the state machines on
//  transitions in and out of host
//  mode. 
assign low_speed_en = hc_ls_timing; 
//  start low speed signalling
assign hc_ls_timing_set = tok_ls_timing_set | txd_ls_timing_set; 
//  end low speed signalling 
assign hc_ls_timing_clr = tok_pstate == TOK_IDLE | txd_pstate == TXD_DONE | 
	txd_pstate == TXD_DELAY ? 1'b 1 : 
	1'b 0; 
//  before Tx Data packet start
assign bdt_wrt_pid = hc_en == 1'b 0 ? current_token : 
	hc_rxd_pid; 
//  Only allow failed data packets that were NAK'ed to auto repeat.
assign hc_no_retry = hc_rxd_pid != PID_NAK ? 1'b 1 : 
	1'b 0; 
//  EMBEDDED HOST REMOVE OFF
// ------------------------------------------------------------------------------
// 
//   Process: sof_regs    -- SOF registers
// 
//   Parameters: clk_sof  -- Clock
// 
//   Description: This process implements the SOF register. This consists of a 
//               host frame timer. The host frame timer has to different modes
//               of operation depending if you are operating in host controller
//               mode or not. When operating in host controller mode (i.e. 
//               hc_en=1) the hc_sof_cnt is used to determine when to issue a
//               SOF. When operating in device mode (i.e. hc_en=0) it is used
//               to determine when to set the sleep interrupt. When it counts 3
//               ms of inactivity the sleep interrupt will be set.
// 
// ------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : sof_regs
   if (rst_a == 1'b 1)
      begin
      sof_cnt_clr <= 1'b 0;	
      hc_sof_tc <= 1'b 0;	
      if (IMPLEMENT_EMBEDED_HOST == 1'b 0)
         begin
         if (lsdev == 1)
            begin
            hc_sof_cnt <= SUSPEND_TERM_CNT_LS;	
            end
         else
            begin
            hc_sof_cnt <= SUSPEND_TERM_CNT_HS;	
            end
         end
      else
         begin
         hc_sof_cnt <= SOF_TERM_CNT_HS;	
         end
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         sof_cnt_clr <= 1'b 0;	
         hc_sof_tc <= 1'b 0;	
         if (hc_en == 1'b 0)
            begin
            if (lsdev == 1)
               begin
               hc_sof_cnt <= SUSPEND_TERM_CNT_LS;	
               end
            else
               begin
               hc_sof_cnt <= SUSPEND_TERM_CNT_HS;	
               end
            end
         else
            begin
            hc_sof_cnt <= SOF_TERM_CNT_HS;	
//  hc_reset is generated from clken of the other clock so it may or may not
//  be around when this reset is active so pull this outside of the clken_12
//  block
            end
         end
//  synchronous resets
      else if (hc_reset == 1'b 1 )
         begin
         hc_sof_cnt <= SOF_TERM_CNT_HS;	
         end
      else if (clken_12 == 1'b 1 )
         begin
         sof_cnt_clr <= sof_cnt_clra;	
//  If not in host controller mode operate as a USB sleep counter
         if (hc_en == 1'b 0)
            begin
            if (sof_cnt_clr == 1'b 1)
               begin
               if (lsdev == 1)
                  begin
                  hc_sof_cnt <= SUSPEND_TERM_CNT_LS;	
                  end
               else
                  begin
                  hc_sof_cnt <= SUSPEND_TERM_CNT_HS;	
                  end
               end
            else if (hc_sof_cnt != {8'b 11111111, 8'b 11111111} )
               begin
               hc_sof_cnt <= hc_sof_cnt - 1'b 1;	
               end
            else
               begin
               hc_sof_cnt <= hc_sof_cnt;	
//  We are operating in host controller mode run as a SOF frametimer
               end
            end
         else
            begin
            if (det_rst == 1'b 1 | hc_sof_cnt == {8'b 11111111, 
	8'b 11111111})
               begin
               hc_sof_cnt <= SOF_TERM_CNT_HS;	
               end
            else
               begin
               hc_sof_cnt <= hc_sof_cnt - 1'b 1;	
               end
            end
//  generate a minimum two cycle wide terminal count to pass from the clken12 
//  domain to the clken_dpll domain.
         if (hc_sof_cnt[15:1] == {8'b 00000000, 7'b 0000000})
            begin
            hc_sof_tc <= 1'b 1;	
            end
         else if (hc_sof_req_set == 1'b 1 | hc_en == 1'b 0 )
            begin
            hc_sof_tc <= 1'b 0;	//  in the clken_dpll domain.
            end
//  hold until registered
         end
      end
//  clk_sof'event and (clk_sof = '1') then
   end
//  generate a two cycle wide terminal count to pass from the clken12 domain to
//  the clken_dpll domain.
assign hc_sof_err_set = hc_sof_req == 1'b 1 & hc_sof_req_f == 1'b 0 & 
	tok_pstate != TOK_IDLE ? hc_en : 
	1'b 0; 
//  issue an error interrupt if a transfer is in progress
//  when the SOF packet is supposed to be sent.
//  In host mode set the sof interrupt when the SOF threshold is reached 
assign hc_sof_thld_set = hc_en == 1'b 1 & hc_token_inhibit == 1'b 1 & 
	hc_token_inhibit_f == 1'b 0 & clk_en == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  single ended zeros are used to signal reset and end of packet
assign usb_se0_req = txd_pstate == TXD_EOP | tok_pstate == TOK_EOP & 
	hc_en == 1'b 1 & zero_stuff == 1'b 0 | 
	hc_rst_req == 1'b 1 & hc_en == 1'b 1 | 
	lseop_en == 1'b 1 & hc_en == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  The J-state is the idle state on usb.
assign usb_jstate_req = resume_req_ff == 1'b 0 & (txd_pstate == TXD_WAIT | 
	txd_pstate == TXD_DELAY | txd_pstate == TXD_HSHK | 
	txd_pstate == TXD_DONE) & ~(hc_en == 1'b 1 & 
	~(tok_pstate == TOK_IDLE | tok_pstate == TOK_PROC | 
	tok_pstate == TOK_WAIT)) | hc_en == 1'b 1 & 
	hc_ls_timing == 1'b 0 & low_speed_req == 1'b 1 & 
	hc_sof_req == 1'b 0 & (tok_pstate == TOK_BYTE0 | 
	txd_pstate == TXD_LSDLY) ? 1'b 1 : 
	1'b 0; 
// (rst = '1') or 
//  The K-state is the resume state on usb.
assign usb_kstate_req = resume_req_ff == 1'b 1 ? 1'b 1 : 
	1'b 0; 
//  USB output enable data
assign usboe_nxt = txd_usboe | resume_req_f | hc_en & (hc_rst_req | 
	lseop_en_nxt | tok_usboe); 
//  USB data minus out data
//  low_speed_signaling - This signal causes the SIE to invert the
//                signaling of the J and K bus states for low speed signalling.
assign idmo_d = usb_se0_req == 1'b 1 | low_speed_signaling == 1'b 0 & 
	usb_jstate_req == 1'b 1 | low_speed_signaling == 1'b 1 & 
	usb_kstate_req == 1'b 1 ? 1'b 0 : 
	low_speed_signaling == 1'b 1 & usb_jstate_req == 1'b 1 | 
	low_speed_signaling == 1'b 0 & usb_kstate_req == 1'b 1 ? 1'b 1 : 
	~usb_nrzo; 
//  USB data plus out data
assign idpo_d = usb_se0_req == 1'b 1 | low_speed_signaling == 1'b 1 & 
	usb_jstate_req == 1'b 1 | low_speed_signaling == 1'b 0 & 
	usb_kstate_req == 1'b 1 ? 1'b 0 : 
	low_speed_signaling == 1'b 0 & usb_jstate_req == 1'b 1 | 
	low_speed_signaling == 1'b 1 & usb_kstate_req == 1'b 1 ? 1'b 1 : 
	usb_nrzo; 
//  Low speed signaling is true if constant in cfg_usb is true or we are a
//  point to point single port root hub and low_speed_req is true.
assign low_speed_signaling = lsdev == 1 ? 1'b 1 : 
	hc_en == 1'b 1 & host_wo_hub == 1'b 0 ? 1'b 0 : 
	low_speed_req; //  this term allow devices to become
//  low speed under software control
//  USB data dout
//  This is the USB serial transmit data that must be NRZI encoded.
assign usb_dout = zero_stuff == 1'b 1 ? 1'b 0 : 
	txd_pstate == TXD_CRC16L | txd_pstate == TXD_CRC16H ? ~crc16_data[15] : 
	crc5_data_se == 1'b 1 ? ~crc5_data[4] : 
	par2ser_rg[0]; 
assign usb_nrzo = usb_dout == 1'b 1 ? idpo : 
	~idpo; 
//  Current token register write data
assign pid_field = {ser2par_rg[4], ser2par_rg[5], ser2par_rg[6], ser2par_rg[7]}; 
assign current_token_d = hc_en == 1'b 1 ? hc_token_pid : 
	current_token_ld == 1'b 1 & pid_chk_ok == 1'b 1 & 
	valid_sof_pid_d == 1'b 0 ? pid_field : 
	current_token_ld == 1'b 1 & pid_chk_ok == 1'b 0 ? 4'b 0000 : 
	current_token; 
//  Current endpoint register write data
assign current_endpt_d = hc_en == 1'b 1 ? 4'b 0000 : 
	current_endpt_ld == 1'b 1 & sof_pid == 1'b 0 ? {ser2par_rg[0], 
	ser2par_rg[1], ser2par_rg[2], ser2par_rg[3]} : 
	current_endpt; 
//   ser2par_rg(5) & ser2par_rg(6) & ser2par_rg(7) & 
//   ser2par_rg(8) when current_endpt_ld = '1' else 
//   current_endpt;
//  Out data01 pid register
//  Store SETUP and Rx Data Packet data pid values.
assign out_data01_pid_d = txd_pstate == TXD_WAIT & rxd_pstate == RXD_PID & 
	ser2par_cnt_eq7 == 1'b 1 ? ser2par_rg[4] : 
	out_data01_pid; 
//  Current frame number write data
//  In device mode capture the frame number.
assign frame_num_d = frame_num_ld == 1'b 1 & hc_en == 1'b 0 ? {ser2par_rg[6], 
	ser2par_rg[7], ser2par_rg[8], ser2par_rg[9], ser2par_rg[10], 
	ser2par_rg[11], ser2par_rg[12], ser2par_rg[13], ser2par_rg[14], 
	ser2par_rg[15], ser2par_rg[16]} : 
	hc_sof_req == 1'b 1 & hc_sof_req_f == 1'b 0 ? frame_num + 
	1 : 
	frame_num; 
//  in host mode increment the frame number.
//  on rising edge of request.
// ------------------------------------------------------------------------------
//  SIE counter signals
// ------------------------------------------------------------------------------
//  NOTE: After plug fest might want to investigate if usb_sie can get away with
//        only one counter to check for resets, bit_stuff, and bto's!
//  Counter data
// cnt_d <= "00000" when srst = '1' or (cnt_en = '1' and cnt_en_d1 = '0') else
//          unsigned(cnt) + 1 when cnt_en = '1' else
//    cnt -- No change
//  Misc Counter clear
//  This counter times 3 different events
//   1) USB resets is SE0 is asserted for 2.5 us.
//   2) USB attach is SE0 is false and rcv doesn't move for 2.5 us
//   3) USB Buss Time Out (BTO) if the bus is idle for 2.5 us when expecting rcv
//      data or acknoledge.
//   4) USB LS EOP: When in host controller mode this counter is used to 
//      generate a LS EOP to terminate resume signaling.
//  In any of these cases the counter is enabled when there are no transitions
//  and is cleared on a transition.
assign mcek_cnt_clr = ~lseop_en & (usboe_i | se0 ^ se0_f) | 
	~se0 & ~se0_f & (jstate ^ jstate_f); //  a transition on the USB siganls
//  is cleared.
//  USB RESET counter
//  restarts the BTO and ATTACH counter
// cnt_en <= '1' when det_se0 = '1' or (rxd_pstate = RXD_IDLE) else
//           '0'; 
// ------------------------------------------------------------------------------
//  CRC5 logic
// ------------------------------------------------------------------------------
assign crc5_okay = crc5_data == 5'b 01100 ? 1'b 1 : 
	1'b 0; 
assign crc5_data_ld = ser2par_rg_se; 
//  shift the crc data out in hc mode into the crc5 field
assign crc5_data_se = hc_en == 1'b 1 & tok_pstate == TOK_BYTE1 & 
	(ser2par_cnt[2] == 1'b 1 | ser2par_cnt[1] == 1'b 1 & 
	ser2par_cnt[0] == 1'b 1) ? 1'b 1 : 
	1'b 0; 
assign crc5_data_clr = tok_pstate == TOK_PID ? 1'b 1 : 
	1'b 0; 
//  This logic will set nxt_crc5_data=1f\h when we detect a flag else it
//  will compute the crc value.
//  Compute next crc high data byte
assign nxt_crc5_data = crc5_data_clr == 1'b 1 ? 5'b 11111 : 
	crc5_data_se == 1'b 1 ? {crc5_data[3:0], 1'b 1} : 
	{crc5_data[3], crc5_data[2], (crc5_data[1] ^ crc5_data[4] ^ 
	usb_crc_data), crc5_data[0], (usb_crc_data ^ crc5_data[4])}; //  bit 0
//  shift enable
//  Compute crc data
//  bit 4
//  bit 3
//  bit 2
//   (crc5_data(1) xor crc5_data(4) xor ser2par_rg(0)) &  -- bit 2
//  bit 1
//   (ser2par_rg(0) xor crc5_data(4)); -- bit 0
// ------------------------------------------------------------------------------
//  CRC16 logic
// ------------------------------------------------------------------------------
assign crc16_okay = crc16_data == 16'b 1000000000001101 ? 1'b 1 : 
	1'b 0; 
//  CRC16 data load enable when srst active, during data control state Tx_OFLG, 
//  or when crc_data_comp oTx_DATA, 
//  Tx_CRCL, and Tx_CRCH.
assign crc16_data_ld = txd_pstate == TXD_PID | rxd_pstate == RXD_PID | 
	ser2par_rg_se == 1'b 1 & (crc16_data_comp == 1'b 1 | 
	crc16_data_se == 1'b 1) ? 1'b 1 : 
	1'b 0; 
//  CRC16 data compute enable during data control state Tx_DATA.
assign crc16_data_comp = rxd_pstate == RXD_BYTE0 | rxd_pstate == RXD_BYTE1 | 
	rxd_pstate == RXD_BYTE2 | txd_pstate == TXD_DATA ? 1'b 1 : 
	1'b 0; 
//  CRC16 data shift enable during tx data packet states TXD_CRC16L or TXD_CRC16H.
assign crc16_data_se = txd_pstate == TXD_CRC16L | txd_pstate == TXD_CRC16H ? 1'b 1 : 
	1'b 0; 
//   (bit_stuff_en = '0' and ((dtx_ctl_pres_state = Tx_CRCL) or 
//   (dtx_ctl_pres_state = Tx_CRCH))) else '0';
//  This logic computes the next CRC data based on CRC data shift enable, CRC
//  data compute enable else it loads FFFF\h.
//  Compute next crc data
assign nxt_crc16_data = crc16_data_se == 1'b 1 ? {crc16_data[14:0], 1'b 1} : 
	crc16_data_comp == 1'b 1 ? comp_crc16_data : 
	16'b 1111111111111111; //  Else force to 1F\h
//  Shift out CRC data
//  Compute CRC data
//  Compute crc data
//  This logic will compute the crc on transmitted data.
assign comp_crc16_data = {(crc16_data[14] ^ crc16_data[15] ^ usb_crc_data), crc16_data[13], 
	crc16_data[12], crc16_data[11], crc16_data[10], crc16_data[9], 
	crc16_data[8], crc16_data[7], crc16_data[6], crc16_data[5], 
	crc16_data[4], crc16_data[3], crc16_data[2], (crc16_data[1] ^ 
	crc16_data[15] ^ usb_crc_data), crc16_data[0], (usb_crc_data ^ 
	crc16_data[15])}; //  bit 0
//  bit 15
//  bit 14
//  bit 13
//  bit 12
//  bit 11
//  bit 10
//  bit 9
//  bit 8
//  bit 7
//  bit 6
//  bit 5
//  bit 4
//  bit 3
//  bit 2
//  bit 1
// ------------------------------------------------------------------------------
// 
//      Process: tok_nsl          -- Token state machine next state logic
// 
//  Parameters:  tok_pstate       -- Token state machine present state bits
//               crc5_okay        -- CRC5 okay
//               det_eop          -- Detect end of packet
//               det_se0          -- Detect single ended zero
//               det_sync         -- Detect USB sync
//               rcv              -- USB Receive Data
//               reject_rx_dat_set -- Reject rx data packet enable--              
//               reject_tx_dat_set  -- Reject tx data packet enable
//               rx_datpkt_done   -- Rx Data Packet process done
//               ser2par_cnt      -- Serial to parallel bit count
//               ser2par_cnt_eq7  -- Serial to parallel bit count equals 7
//               sof_pid          -- SOF pid detect
//               token_proc_en    -- Token processing enable
//               tx_datpkt_done    -- Tx Data Packet process done
//               usb_addr_eq      -- USB address equals
//               valid_token_pid  -- Valid token PID
// 
//  Description: This process implements next state logic for the token
//   processing state machine.
// 
//  State Diagram: TBD
// 
// ------------------------------------------------------------------------------
always @(bdt_valid or bit_stuff_err or crc5_okay or current_token or det_eop
 or det_se0 or det_sync or dma_re_rd_bdt or hc_en or hc_ls_timing
 or hc_sof_req or hc_token_busy or hc_token_inhibit or low_speed_req or hc_no_retry
 or hc_retry_disable or host_wo_hub or own_d or own_ok or rcv
 or reject_rx_datpkt or reject_tx_datpkt or rx_datpkt_done or rxd_pstate or ser2par_cnt
 or ser2par_cnt_eq1 or ser2par_cnt_eq7 or sof_pid or tok_pstate or token_proc_en
 or tx_datpkt_done or txd_pstate or usb_addr_eq or valid_token_pid or usboe_early_r1)
   begin : tok_nsl
   tok_nstate <= TOK_IDLE;	
   dev_dma_rd_bdt <= 1'b 0;	//  device DMA read BDT (4 bytes) 
   dma_wrt_bdt <= 1'b 0;	//  DMA write BDT (4 bytes)
   hc_token_done <= 1'b 0;	//  embedded host token transaction complete
   txd_suspend_set <= 1'b 0;	//  set the transmit suspend register.
   endpt_stall_clr <= 1'b 0;	//  clear the protocol stall on receipt
   dfn8_err_tok <= 1'b 0;	//  don't set the dfn8 error indication
   tok_ls_timing_set <= 1'b 0;	//  leave the low speed timing alone.
//  Load current frame number register
   frame_num_ld <= 1'b 0;	
   tok_usboe <= 1'b 0;	
//  When present state is token idle state
   case (tok_pstate)
   TOK_IDLE:
      begin
      if (hc_en == 1'b 1)
         begin
         if (txd_pstate == TXD_WAIT & rxd_pstate == RXD_WAIT & 
	(hc_token_busy == 1'b 1 & hc_token_inhibit == 1'b 0 & 
	own_d == 1'b 1 & bdt_valid == 1'b 1 | 
	hc_sof_req == 1'b 1))
            begin
            tok_usboe <= 1'b 1;	
            if (usboe_early_r1 == 1'b 1)
               begin
               tok_nstate <= TOK_SYNC;	//  Goto token sync state
               end
//  hold off until usboe_early pulse is generated
            else
               begin
               tok_nstate <= TOK_IDLE;	//  Stay here
//  no host requsests active
               end
            end
         else
            begin
            tok_nstate <= TOK_IDLE;	//  Stay here
//  target / device operation
//  If detect a change on rcv
            end
//  hc_token_busy
         end
//  host operation
      else
         begin
         if (rcv == 1'b 0)
            begin
            tok_nstate <= TOK_SYNC;	//  Goto token sync state
            end
         else
            begin
            tok_nstate <= TOK_IDLE;	//  Stay here
            end
         end
//  hc_en
//  When present state is token sync state
      end
   TOK_SYNC:
      begin
      if (hc_en == 1'b 1)
         begin
         tok_usboe <= 1'b 1;	
         if (ser2par_cnt_eq7 == 1'b 1)
            begin
            tok_nstate <= TOK_PID;	//  Goto token wait state
            end
         else
            begin
            tok_nstate <= TOK_SYNC;	//  Stay here
//  target / device operation
//  If false eop abort token
            end
//  ser2par_cnt_eq7
         end
//  host operation
      else
         begin
         if (det_se0 == 1'b 1)
            begin
            tok_nstate <= TOK_WAIT;	//  Goto token wait state
//  If detect a sync
            end
         else if (det_sync == 1'b 1 )
            begin
            tok_nstate <= TOK_PID;	//  Goto token pid state
            end
         else
            begin
            tok_nstate <= TOK_SYNC;	//  Stay here
            end
         end
//  hc_en
//  When present state is token pid state
      end
   TOK_PID:
      begin
      if (hc_en == 1'b 1)
         begin
         tok_usboe <= 1'b 1;	
         if (ser2par_cnt_eq7 == 1'b 1)
            begin
            tok_nstate <= TOK_BYTE0;	//  Goto token byte0 state
            end
         else
            begin
            tok_nstate <= TOK_PID;	//  Stay here
//  target / device operation
//  If false eop or not a valid token equal abort token
            end
//  ser2par_cnt_eq7
         end
//  host operation
      else
         begin
         if (det_se0 == 1'b 1 | ser2par_cnt_eq7 == 1'b 1 & 
	valid_token_pid == 1'b 0 | bit_stuff_err == 1'b 1)
            begin
            tok_nstate <= TOK_WAIT;	//  Goto token wait state
            if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 0)
               begin
               dfn8_err_tok <= 1'b 1;	//  set the dfn8 error indication
//  Make sure we have received a valid token
               end
            end
//  bit stuff error
         else if (ser2par_cnt_eq7 == 1'b 1 & valid_token_pid == 1'b 1 )
            begin
            tok_nstate <= TOK_BYTE0;	//  Goto token byte0 state
            end
         else
            begin
            tok_nstate <= TOK_PID;	//  Stay here
            end
         end
//  hc_en
//  When present state is token byte0 state
      end
   TOK_BYTE0:
      begin
      if (hc_en == 1'b 1)
         begin
         tok_usboe <= 1'b 1;	
//  when operating as a host with a hub.  To support low speed devices
//  through a hub, the TOK state machine sends a sync and a PRE_PID 
//  at high speed.  Then is switches the speed to low speed and starts
//  the transaction again from the TOK sync state.  The hc_sof_req term
//  prevents SOF packets from being sent at low speed.
         if (host_wo_hub == 1'b 0 & hc_ls_timing == 1'b 0 & 
	low_speed_req == 1'b 1 & ser2par_cnt_eq7 == 1'b 1 & 
	hc_sof_req == 1'b 0)
            begin
            tok_nstate <= TOK_SYNC;	
            tok_ls_timing_set <= 1'b 1;	
            end
         else if (ser2par_cnt_eq7 == 1'b 1 )
            begin
            tok_nstate <= TOK_BYTE1;	//  Goto token byte1 state
            end
         else
            begin
            tok_nstate <= TOK_BYTE0;	//  Stay here
//  target / device operation
//  If false eop or usb address not equal abort token
            end
//  ser2par_cnt_eq7
         end
//  host operation
      else
         begin
         if (det_se0 == 1'b 1 | bit_stuff_err == 1'b 1)
            begin
            tok_nstate <= TOK_WAIT;	//  Goto token wait state
            if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 0)
               begin
               dfn8_err_tok <= 1'b 1;	//  set the dfn8 error indication
               end
            end
         else if (ser2par_cnt_eq7 == 1'b 1 )
            begin
            tok_nstate <= TOK_BYTE1;	//  Goto token byte1 state
            end
         else
            begin
            tok_nstate <= TOK_BYTE0;	//  Stay here
            end
         end
//  hc_en
//  When present state is token byte1 state
      end
   TOK_BYTE1:
      begin
      if (hc_en == 1'b 1)
         begin
         tok_usboe <= 1'b 1;	
         if (ser2par_cnt_eq7 == 1'b 1)
            begin
            tok_nstate <= TOK_EOP;	//  Goto token eop state
            end
         else
            begin
            tok_nstate <= TOK_BYTE1;	//  Stay here
//  target / device operation
            end
//  ser2par_cnt_eq7
         end
//  host operation
      else
         begin
         if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 0)
            begin
            tok_nstate <= TOK_WAIT;	//  Goto token wait state
            if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 0)
               begin
               dfn8_err_tok <= 1'b 1;	//  set the dfn8 error indication
               end
            end
//  False eop
         else if (bit_stuff_err == 1'b 1 )
            begin
            tok_nstate <= TOK_WAIT;	//  Goto token wait state
            end
         else if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 1 )
            begin
            tok_nstate <= TOK_EOP;	//  Goto token eop state
            end
         else
            begin
            tok_nstate <= TOK_BYTE1;	//  Stay here
            end
         end
//  hc_en
//  When present state is token eop state
      end
   TOK_EOP:
      begin
      if (hc_en == 1'b 1)
         begin
         if (ser2par_cnt_eq1 == 1'b 1)
            begin
            if (hc_sof_req == 1'b 1)
               begin
               tok_nstate <= TOK_IDLE;	//  Goto token idle state
               end
            else
               begin
               tok_nstate <= TOK_PROC;	//  Goto token process state
               end
// 
            end
         else
            begin
            tok_usboe <= 1'b 1;	
            tok_nstate <= TOK_EOP;	//  Stay here
//  target / device operation
//  Wait for EOP
            end
//  ser2par_cnt_eq7
         end
//  host operation
      else
         begin
         if (det_eop == 1'b 1)
            begin
            if (sof_pid == 1'b 1 & crc5_okay == 1'b 1 & 
	bit_stuff_err == 1'b 0)
               begin
               frame_num_ld <= 1'b 1;	//  Load current frame number register
               tok_nstate <= TOK_IDLE;	//  Goto token idle state
               end
            else if (token_proc_en == 1'b 1 & usb_addr_eq == 1'b 1 & 
	crc5_okay == 1'b 1 & bit_stuff_err == 1'b 0 )
               begin
               dev_dma_rd_bdt <= ~own_ok | dma_re_rd_bdt;	// or the DMA values need to be re-read.
               if (current_token == PID_SETUP)
                  begin
                  endpt_stall_clr <= 1'b 1;	//  clear the protocol stall on receipt
//  of a valid SETUP token.
                  end
//  may need to add OUT tokens also
               tok_nstate <= TOK_PROC;	//  Goto token process state
               end
            else
               begin
               tok_nstate <= TOK_IDLE;	//  Goto token idle state
//  We only want to wait for the EOP for a short
//  period of time, if we do not get it return to IDLE
               end
            end
         else if (ser2par_cnt[2] == 1'b 1 )
            begin
            tok_nstate <= TOK_IDLE;	//  Goto token idle state
            end
         else
            begin
            tok_nstate <= TOK_EOP;	//  Stay here
            end
         end
//  hc_en
//  When present state is token process state
      end
   TOK_PROC:
      begin
      if (tx_datpkt_done == 1'b 1 | rx_datpkt_done == 1'b 1)
         begin
         if (reject_tx_datpkt == 1'b 1 | reject_rx_datpkt == 1'b 1)
            begin
            if (hc_en == 1'b 1)
               begin
               if (hc_no_retry == 1'b 1 | hc_retry_disable == 1'b 1)
                  begin
                  dma_wrt_bdt <= 1'b 1;	//  Write the recieved PID out to the
                  hc_token_done <= 1'b 1;	//  BDT control word
                  end
//  as a host don't repeat failed transaction automatically when
//  no retry is set or the failure is not retry worthy.
               end
//  if operating as a host
            tok_nstate <= TOK_IDLE;	//  Transmission failed
//  If the packet is OK write the BDT
            end
         else
            begin
            dma_wrt_bdt <= 1'b 1;	//  DMA write BDT (4 bytes)
            tok_nstate <= TOK_IDLE;	//  Goto token idle state
            if (hc_en == 1'b 1)
               begin
               hc_token_done <= 1'b 1;	
               end
            else if (current_token == PID_SETUP )
               begin
               txd_suspend_set <= 1'b 1;	//  hold off any new tokens until
//  software catches up.
               end
            end
         end
      else
         begin
         tok_nstate <= TOK_PROC;	//  Stay here
//  When present state is token wait state
         end
      end
//  If the in or rx data packet state machines reject a token for any reason
//  the token processing state machine must return to idle
   TOK_WAIT:
      begin
      if (det_eop == 1'b 1)
         begin
         tok_nstate <= TOK_IDLE;	//  Goto token idle state
         end
      else
         begin
         tok_nstate <= TOK_WAIT;	//  Stay here
//  Default next state, eliminates feedback loops
         end
      end
   default:
      begin
      tok_nstate <= TOK_IDLE;	
      end
   endcase
   end
// ------------------------------------------------------------------------------
// 
//      Process: txd_nsl           -- Tx Data Packet state machine next state logic
// 
//   Parameters: txd_pstate        -- Tx Data Packet state machine present state bits
//               tx_datpkt_proc     -- Tx Data Packet process
//               out_handshake_en  -- Out handshake enable
//               ser2par_cnt_eq2   -- Serial to parallel bit count equals 2
//               ser2par_cnt_eq7   -- Serial to parallel bit count equals 7
//               endpt_hshk        -- Endpoint hand shake enable
//               own               -- BDT own control bit
//               transmit_done     -- Transmit done
//               in_handshake_done -- In handshake done
//               last_bit_stuff_en -- Last bit stuff enable
// 
//  Description: This process implements next state logic for the tx data packet
//   processing state machine.
// 
//  State Diagram: TBD
// 
// ------------------------------------------------------------------------------
//  SIE DMA requests default output values
always @(txd_pstate or tx_datpkt_proc or out_handshake_en or ser2par_cnt_eq1 or ser2par_cnt_eq7
 or endpt_hshk or own or hc_en or hc_ls_timing or low_speed_req
 or endpt_stall or byte_count_eq or in_handshake_done or transmit_done or last_bit_stuff_en
 or zero_stuff_inhibit or host_wo_hub)
   begin : txd_nsl
   out_handshake_done <= 1'b 0;	//  Default output value
   start_txd <= 1'b 0;	//  Default output value
   txd_ls_timing_set <= 1'b 0;	//  by default leave the low speed timing alone.
   txd_usboe <= 1'b 0;	
//  When present state is tx data packet wait state
   case (txd_pstate)
   TXD_WAIT:
      begin
      if (tx_datpkt_proc == 1'b 1 | out_handshake_en == 1'b 1)
         begin
         start_txd <= 1'b 1;	//  Signal sie logic that we are starting a tx data packet
         txd_usboe <= 1'b 1;	
         txd_nstate <= TXD_SYNC;	//  Goto tx data packet sync state
//         txd_nstate <= TXD_DELAY; -- Goto tx data packet delay state
         end
      else
         begin
         txd_nstate <= TXD_WAIT;	//  Stay here
//  When present state is tx data packet wait state
         end
      end
//  If detect a tx data packet process
   TXD_DELAY:
      begin
      start_txd <= 1'b 1;	//  Signal sie logic that we are starting
//  a tx data packet
      txd_nstate <= TXD_SYNC;	//  Goto tx data packet sync state
//  When present state is tx data packet sync state
      end
//  If detect a tx data packet process
   TXD_SYNC:
      begin
      txd_usboe <= 1'b 1;	
      if (ser2par_cnt_eq7 == 1'b 1)
         begin
         if (hc_en == 1'b 1 & host_wo_hub == 1'b 0 & 
	hc_ls_timing == 1'b 0 & low_speed_req == 1'b 1)
            begin
            txd_nstate <= TXD_PRE;	
            end
         else
            begin
            txd_nstate <= TXD_PID;	//  Goto tx data packet pid state
            end
         end
//  If this is a host sending to a low speed device and the
//  timing has not yet been switched to low speed. Go to the
//  send a PRE pid state.
      else
         begin
         txd_nstate <= TXD_SYNC;	//  Stay here
//  When present state is tx data packet PRE pid state
         end
      end
//  Transmit a sync
   TXD_PRE:
      begin
      txd_usboe <= 1'b 1;	
//  Transmit a PRE PID
      if (ser2par_cnt_eq7 == 1'b 1)
         begin
         txd_nstate <= TXD_LSDLY;	//  Go to Low Speed delay
         end
      else
         begin
         txd_nstate <= TXD_PRE;	//  Stay here finish sending PRE pid
//  When present state is low speed delay
         end
      end
   TXD_LSDLY:
      begin
      txd_usboe <= 1'b 1;	
//  Wait before switching the clock to low speed.
      if (ser2par_cnt_eq7 == 1'b 1)
         begin
         txd_nstate <= TXD_SYNC;	//  Start sending Low Speed Sync
         txd_ls_timing_set <= 1'b 1;	
         end
      else
         begin
         txd_nstate <= TXD_LSDLY;	//  Stay here and wait
//  When present state is tx data packet pid state
         end
      end
   TXD_PID:
      begin
      txd_usboe <= 1'b 1;	
//  Transmit a PID
      if (ser2par_cnt_eq7 == 1'b 1)
         begin
         if (endpt_stall == 1'b 1 | out_handshake_en == 1'b 1)
            begin
            txd_nstate <= TXD_EOP;	//  Handshake was sent; Goto eop state
//  Check for NAK condition
            end
         else if (own == 1'b 0 )
            begin
            if (endpt_hshk == 1'b 0)
               begin
               txd_nstate <= TXD_CRC16L;	//  Sent a zero length ISO Pkt
//  Non-ISO endpoint
               end
//  ISO endpoint?
            else
               begin
               txd_nstate <= TXD_EOP;	//  NAK was sent; goto eop state
               end
            end
//  BDT not ready
         else
            begin
            if (transmit_done == 1'b 0)
               begin
               txd_nstate <= TXD_DATA;	//  Goto tx data byte state
               end
            else
               begin
               txd_nstate <= TXD_CRC16L;	//  Goto tx data packet CRC16L state
               end
            end
         end
//  Check for STALL, or handshake condition
      else
         begin
         txd_nstate <= TXD_PID;	//  Stay here
//  When present state is tx data packet data state
         end
      end
   TXD_DATA:
      begin
      txd_usboe <= 1'b 1;	
//  Transmit a data
      if (ser2par_cnt_eq7 == 1'b 1 & zero_stuff_inhibit == 1'b 1)
         begin
         txd_nstate <= TXD_EOP;	//  After forcing a bit stuff error end packet
         end
      else if (ser2par_cnt_eq7 == 1'b 1 & transmit_done == 1'b 1 )
         begin
         txd_nstate <= TXD_CRC16L;	//  Goto tx data packet crc16l state
         end
      else
         begin
         txd_nstate <= TXD_DATA;	//  Stay here
//  When present state is tx data packet crc16l state
         end
      end
   TXD_CRC16L:
      begin
      txd_usboe <= 1'b 1;	
//  Transmit low order byte of crc16
      if (ser2par_cnt_eq7 == 1'b 1)
         begin
         txd_nstate <= TXD_CRC16H;	//  Goto tx data packet crc16h state
         end
      else
         begin
         txd_nstate <= TXD_CRC16L;	//  Stay here
//  When present state is tx data packet crc16h state
         end
      end
   TXD_CRC16H:
      begin
      txd_usboe <= 1'b 1;	
//  Transmit high order byte of crc16
      if (last_bit_stuff_en == 1'b 1)
         begin
         txd_nstate <= TXD_LBS;	//  Goto tx data packet last bit stuff state
         end
      else if (ser2par_cnt_eq7 == 1'b 1 )
         begin
         txd_nstate <= TXD_EOP;	//  Goto tx data packet eop state
         end
      else
         begin
         txd_nstate <= TXD_CRC16H;	//  Stay here
//  Special state to force the insertion of a bit stuff after CRC
         end
      end
   TXD_LBS:
      begin
      txd_usboe <= 1'b 1;	
      txd_nstate <= TXD_EOP;	//  Goto tx data packet eop state
//  When present state is tx data packet eop state
      end
   TXD_EOP:
      begin
      if (ser2par_cnt_eq1 == 1'b 1)
         begin
         if (own == 1'b 0 | endpt_stall == 1'b 1 | 
	endpt_hshk == 1'b 0 | out_handshake_en == 1'b 1)
            begin
            txd_nstate <= TXD_DONE;	//  Iso endpoint (hand shake disabled) goto 
//  tx data packet done state
            end
         else
            begin
            txd_nstate <= TXD_HSHK;	//  Goto tx data packet handshake state
            end
         end
      else
         begin
         txd_usboe <= 1'b 1;	
         txd_nstate <= TXD_EOP;	//  Stay here
//  When present state is tx data packet handshake state
         end
      end
//  Transmit a EOP
//       if ser2par_cnt_eq2 = '1' then 
   TXD_HSHK:
      begin
      if (in_handshake_done == 1'b 1)
         begin
         txd_nstate <= TXD_DONE;	//  Goto tx data packet done state
         end
      else
         begin
         txd_nstate <= TXD_HSHK;	//  Stay here
//  When present state is tx data packet done state
         end
      end
   TXD_DONE:
      begin
      out_handshake_done <= 1'b 1;	//  Rx Data Packet handshake done
      txd_nstate <= TXD_WAIT;	//  Goto tx data packet wait state
//  Default next state, eliminates feedback loops
      end
//       tx_datpkt_done <= '1';  -- Tx Data Packet process done
   default:
      begin
      txd_nstate <= TXD_WAIT;	
      end
   endcase
   end
// ------------------------------------------------------------------------------
// 
//      Process: rxd_nsl            -- Rx Data Packet state machine next state logic
// 
//   Parameters: 
//               bit_stuff_err
//               bto_err_set        -- Bus timeout error interrupt set
//               crc16_err_set      -- CRC16 error detected
//               current_token      -- Current token
//               det_eop            -- Detected end of packet
//               det_se0            -- Detected Single ended Zero
//               det_sync           -- Detected USB sync
//               endpt_stall        -- Endpoint stalled
//               endpt_hshk         -- Endpoint hand shake enable
//               in_handshake_en    -- In handshake enable
//               out_handshake_done -- Out handshake done
//               own                -- BDT owned by SIE
//               rcv                -- USB Receive Data
//               rx_datpkt_proc     -- Rx Data Packet process
//               rx_overrun_nak     -- Force a Nak responce to this Rx Packet
//               rxd_pstate         -- Rx Data Packet state machine present state bits
//               ser2par_cnt_eq7    -- Serial to parallel bit count equals 7
//               valid_data_pid     -- Valid data PID
//               valid_data_tgl     -- Valid data toggle bit on this data PID
//               valid_stall_pid    -- Valid data STALL
// 
//  Description: This process implements next state logic for the token
//   processing state machine.
// 
//  State Diagram: TBD
// 
// ------------------------------------------------------------------------------
//   tx_datpkt_done <= '0'; -- Default output value
always @(bit_stuff_err or bto_err_set or crc16_err_set or current_token or det_eop
 or det_se0 or det_sync or endpt_hshk or in_handshake_en or out_handshake_done
 or own or rcv or rx_datpkt_proc or rx_overrun_nak or rxd_pstate
 or ser2par_cnt_eq7 or valid_data_pid or valid_data_tgl or valid_stall_pid)
   begin : rxd_nsl
   in_handshake_done <= 1'b 0;	//  Default output value
   dfn8_err_rxd <= 1'b 0;	//  Default output value
   reject_rx_dat_set <= 1'b 0;	//  Default output value
//  When present state is rx data packet wait state
   case (rxd_pstate)
   RXD_WAIT:
      begin
      if (rx_datpkt_proc == 1'b 1 | in_handshake_en == 1'b 1)
         begin
         rxd_nstate <= RXD_IDLE;	//  Goto rx data packet idle state
         end
      else
         begin
         rxd_nstate <= RXD_WAIT;	//  Stay here
//  When present state is rx data packet idle state
         end
      end
//  If detect a rx data packet process
   RXD_IDLE:
      begin
      if (bto_err_set == 1'b 1)
         begin
         if (endpt_hshk == 1'b 1)
            begin
            reject_rx_dat_set <= 1'b 1;	//  BTO, reject rx data packet
            end
//   ISO packets that BTO just update the BDT.
         rxd_nstate <= RXD_DONE;	//  BTO, goto wait state
//  If detect a change on rcv
         end
      else if (rcv == 1'b 0 )
         begin
         rxd_nstate <= RXD_SYNC;	//  Goto rx data packet sync state
         end
      else
         begin
         rxd_nstate <= RXD_IDLE;	//  Stay here
//  When present state is rx data packet sync state
         end
      end
//  If detect a bus timeout error
   RXD_SYNC:
      begin
      if (det_sync == 1'b 1)
         begin
         rxd_nstate <= RXD_PID;	//  Goto rx data packet pid state
         end
      else if (bto_err_set == 1'b 1 )
         begin
         if (endpt_hshk == 1'b 1)
            begin
            reject_rx_dat_set <= 1'b 1;	//  BTO, reject rx data packet
            end
//   ISO packets that BTO just update the BDT.
         rxd_nstate <= RXD_DONE;	//  BTO, goto wait state
         end
      else
         begin
         rxd_nstate <= RXD_SYNC;	//  Stay here
//  When present state is rx data packet pid state
         end
      end
//  If detect a sync
   RXD_PID:
      begin
      if (bit_stuff_err == 1'b 1)
         begin
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state
//  If false eop
         end
      else if (ser2par_cnt_eq7 == 1'b 0 & det_se0 == 1'b 1 )
         begin
         dfn8_err_rxd <= 1'b 1;	//  Data field not 8-bits error interrupt set
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state
//  If received a byte, 
         end
      else if (ser2par_cnt_eq7 == 1'b 1 )
         begin
         if (in_handshake_en == 1'b 1)
            begin
            rxd_nstate <= RXD_EOP;	//  go directly to EOP
            end
//  if receiving a handshake 
         else
            begin
            if (valid_stall_pid == 1'b 1)
               begin
               rxd_nstate <= RXD_EOP;	//   go directly to EOP
               end
//  if stall
            else if (valid_data_pid == 1'b 1 )
               begin
               if (valid_data_tgl == 1'b 0 & endpt_hshk == 1'b 1 & 
	current_token != PID_SETUP)
                  begin
                  reject_rx_dat_set <= 1'b 1;	//    reject rx data packet, but
//    complete the the packet and send
//    an Acknowledge handshake
                  end
//    and it is not a SETUP packet
//  data toggle
               rxd_nstate <= RXD_BYTE0;	//  Goto rx data packet byte0 state
               end
//  if it is a data pid
            else
               begin
               reject_rx_dat_set <= 1'b 1;	//  PID not valid, reject rx data packet
               rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state
               end
            end
         end
      else
         begin
         rxd_nstate <= RXD_PID;	//  Stay here
//  When present state is rx data packet byte0 state
         end
      end
//  bit stuff error  
   RXD_BYTE0:
      begin
      if (bit_stuff_err == 1'b 1)
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state 
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         end
//  bit stuff error or
      else if (det_se0 == 1'b 1 )
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state 
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         if (ser2par_cnt_eq7 == 1'b 0)
            begin
            dfn8_err_rxd <= 1'b 1;	//  Data field not 8-bits error interrupt set
            end
         end
//       elsif det_eop = '1' then
      else if (ser2par_cnt_eq7 == 1'b 1 )
         begin
         rxd_nstate <= RXD_BYTE1;	//  Goto rx data packet byte1 state
         end
      else
         begin
         rxd_nstate <= RXD_BYTE0;	//  Stay here
//  When present state is rx data packet byte1 state
         end
      end
//  If false eop or usb address not equal abort token 
   RXD_BYTE1:
      begin
      if (bit_stuff_err == 1'b 1)
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state 
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         end
//  bit stuff error or
      else if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 1 )
         begin
         rxd_nstate <= RXD_EOP;	//  Goto rx data packet eop state
         end
//  Detect single ended 0
      else if (det_se0 == 1'b 1 )
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state 
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         dfn8_err_rxd <= 1'b 1;	//  Data field not 8-bits error interrupt set
         end
      else if (ser2par_cnt_eq7 == 1'b 1 )
         begin
         rxd_nstate <= RXD_BYTE2;	//  Goto rx data packet byte2 state
         end
      else
         begin
         rxd_nstate <= RXD_BYTE1;	//  Stay here
//  When present state is rx data packet byte2 state
         end
      end
   RXD_BYTE2:
      begin
      if (bit_stuff_err == 1'b 1)
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet wait state 
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         end
//  bit stuff error or
      else if (det_se0 == 1'b 1 & ser2par_cnt_eq7 == 1'b 1 )
         begin
         rxd_nstate <= RXD_EOP;	//  Goto rx data packet eop state
         end
//  Detect single ended 0
      else if (det_se0 == 1'b 1 )
         begin
         rxd_nstate <= RXD_DONE;	//  Reject rx data packet goto rx data packet wait state
         reject_rx_dat_set <= 1'b 1;	//  not valid, reject rx data packet
         dfn8_err_rxd <= 1'b 1;	//  Data field not 8-bits error interrupt set
         end
//  False eop
      else
         begin
         rxd_nstate <= RXD_BYTE2;	//  Stay here
//  When present state is rx data packet byte2 state
         end
      end
   RXD_EOP:
      begin
      if (crc16_err_set == 1'b 1)
         begin
         rxd_nstate <= RXD_DONE;	//  Abort the rxd packet on crc16 error detect
         reject_rx_dat_set <= 1'b 1;	// reject rx data packet
         end
      else if (det_eop == 1'b 1 & current_token == PID_SETUP & 
	own == 1'b 0 )
         begin
         rxd_nstate <= RXD_DONE;	//  IF you couldn't accept a setup packet then
         reject_rx_dat_set <= 1'b 1;	// reject the rx packet and allow the USB to
//  time out
         end
      else if (det_eop == 1'b 1 & (in_handshake_en == 1'b 1 | 
	endpt_hshk == 1'b 0) )
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet done state, no hand
//  shake is sent.
         end
//  on ISO packets interrupt even if own is 0
      else if (det_eop == 1'b 1 )
         begin
         if (rx_overrun_nak == 1'b 1)
            begin
            reject_rx_dat_set <= 1'b 1;	//  stop the BDT write, but go ahead
            if (current_token == PID_SETUP)
               begin
               rxd_nstate <= RXD_DONE;	//  Goto rx data packet done state, no hand
//  shake is sent.
               end
            else
               begin
               rxd_nstate <= RXD_HSHK;	//  Goto rx data packet handshake state
               end
//  and send a NAK handshake.
            end
//  if non-ISO overrun error
         else
            begin
            rxd_nstate <= RXD_HSHK;	//  Goto rx data packet handshake state
            end
         end
//  otherwise send the appropriate handshake.
      else
         begin
         rxd_nstate <= RXD_EOP;	//  Stay here
//  When present state is rx data packet handshake state
         end
      end
//  Wait for EOP
//  No handshake needed if we meet any of the following conditions
//  Processing SETUP and own=0 or
//  Doing a handshake in response to TX DATA PACKET (in_handshake_en=1)
//  or we are an isochronous endpoint type (endpt_hshk=0)
   RXD_HSHK:
      begin
      if (out_handshake_done == 1'b 1)
         begin
         rxd_nstate <= RXD_DONE;	//  Goto rx data packet done state
         end
      else
         begin
         rxd_nstate <= RXD_HSHK;	//  Stay here
//  When present state is rx data packet done state
         end
      end
   RXD_DONE:
      begin
      in_handshake_done <= 1'b 1;	//  Tx Data Packet handshake done
      rxd_nstate <= RXD_WAIT;	//  Goto rx data packet wait state
//  Default next state, eliminates feedback loops
      end
   default:
      begin
      rxd_nstate <= RXD_WAIT;	
      end
   endcase
   end
// ------------------------------------------------------------------------------
// 
//      Process: tok_monitor
// 
//   Parameters: tok_pstate  -- Token state machine state bits
// 
//  Description: This process monitors the token present state bit and
//   converts them in to an enumerated type. This is helpful when
//   simulating the USB sie because present states information is
//   displayed as the enumerated type instead of a signal.
// 
// ------------------------------------------------------------------------------
always @(tok_pstate)
   begin : tok_monitor
   case (tok_pstate)
   TOK_IDLE:
      begin
      tok_enum <= tok_states_TOK_IDLE_E;	//  When present state is token idle state
//  When present state is token sync state
      end
   TOK_SYNC:
      begin
      tok_enum <= tok_states_TOK_SYNC_E;	
//  When present state is token pid state
      end
   TOK_PID:
      begin
      tok_enum <= tok_states_TOK_PID_E;	
//  When present state is token byte0 state
      end
   TOK_BYTE0:
      begin
      tok_enum <= tok_states_TOK_BYTE0_E;	
//  When present state is token byte1 state
      end
   TOK_BYTE1:
      begin
      tok_enum <= tok_states_TOK_BYTE1_E;	
//  When present state is token eop state
      end
   TOK_EOP:
      begin
      tok_enum <= tok_states_TOK_EOP_E;	
//  When present state is token process state
      end
   TOK_PROC:
      begin
      tok_enum <= tok_states_TOK_PROC_E;	
//  When present state is token wait state
      end
   TOK_WAIT:
      begin
      tok_enum <= tok_states_TOK_WAIT_E;	
//  Default next state
      end
   default:
      begin
      tok_enum <= tok_states_ERROR_E;	
      end
   endcase
   end
// ------------------------------------------------------------------------------
// 
//      Process: txd_monitor
// 
//   Parameters: txd_pstate  -- Tx Data Packet state machine state bits
// 
//  Description: This process monitors the tx data packet present state bit and
//   converts them in to an enumerated type. This is helpful when
//   simulating the USB sie because present states information is
//   displayed as the enumerated type instead of a signal.
// 
// ------------------------------------------------------------------------------
always @(txd_pstate)
   begin : txd_monitor
   case (txd_pstate)
   TXD_WAIT:
      begin
      txd_enum <= txd_states_TXD_WAIT_E;	
      end
   TXD_SYNC:
      begin
      txd_enum <= txd_states_TXD_SYNC_E;	
      end
   TXD_PID:
      begin
      txd_enum <= txd_states_TXD_PID_E;	
      end
   TXD_DATA:
      begin
      txd_enum <= txd_states_TXD_DATA_E;	
      end
   TXD_CRC16L:
      begin
      txd_enum <= txd_states_TXD_CRC16L_E;	
      end
   TXD_CRC16H:
      begin
      txd_enum <= txd_states_TXD_CRC16H_E;	
      end
   TXD_EOP:
      begin
      txd_enum <= txd_states_TXD_EOP_E;	
      end
   TXD_HSHK:
      begin
      txd_enum <= txd_states_TXD_HSHK_E;	
      end
   TXD_DONE:
      begin
      txd_enum <= txd_states_TXD_DONE_E;	
      end
   TXD_DELAY:
      begin
      txd_enum <= txd_states_TXD_DELAY_E;	
      end
   TXD_PRE:
      begin
      txd_enum <= txd_states_TXD_PRE_E;	
      end
   TXD_LSDLY:
      begin
      txd_enum <= txd_states_TXD_LSDLY_E;	
      end
   default:
      begin
      txd_enum <= txd_states_TXD_WAIT_E;	
      end
   endcase
   end
// ------------------------------------------------------------------------------
// 
//      Process: rxd_monitor
// 
//   Parameters: rxd_pstate  -- Rx Data Packet state machine state bits
// 
//  Description: This process monitors the rx data packet present state bit and
//   converts them in to an enumerated type. This is helpful when
//   simulating the USB sie because present states information is
//   displayed as the enumerated type instead of a signal.
// 
// ------------------------------------------------------------------------------
always @(rxd_pstate)
   begin : rxd_monitor
   case (rxd_pstate)
   RXD_WAIT:
      begin
      rxd_enum <= rxd_states_RXD_WAIT_E;	
      end
   RXD_IDLE:
      begin
      rxd_enum <= rxd_states_RXD_IDLE_E;	
      end
   RXD_SYNC:
      begin
      rxd_enum <= rxd_states_RXD_SYNC_E;	
      end
   RXD_PID:
      begin
      rxd_enum <= rxd_states_RXD_PID_E;	
      end
   RXD_BYTE0:
      begin
      rxd_enum <= rxd_states_RXD_BYTE0_E;	
      end
   RXD_BYTE1:
      begin
      rxd_enum <= rxd_states_RXD_BYTE1_E;	
      end
   RXD_BYTE2:
      begin
      rxd_enum <= rxd_states_RXD_BYTE2_E;	
      end
   RXD_EOP:
      begin
      rxd_enum <= rxd_states_RXD_EOP_E;	
      end
   RXD_HSHK:
      begin
      rxd_enum <= rxd_states_RXD_HSHK_E;	
      end
   RXD_DONE:
      begin
      rxd_enum <= rxd_states_RXD_DONE_E;	
      end
   default:
      begin
      rxd_enum <= rxd_states_RXD_WAIT_E;	
      end
   endcase
   end

//  The following were added to support SLOW and FULL SUSPEND of 3ms

endmodule // module vusb_sie