// jctrl.v v1 Frank Berndt
// joychannel behavioral model;
// :set tabstop=4

`timescale 1ns/10ps

module jctrl (
	jbus
);
	inout jbus;

	// optionally turn on controller monitor;

	reg jctrl_mon;				// controller monitor flag;

	// jbus timing;

`include "jctrl.vh"
`define	TMAX_GLITCH	100			// max glitch time in ns;
`define	TMIN_TS		64000		// min transfer separator signal;
`define	TMAX_TC		64000		// max transfer continuous signal;
`define	TMAX_SR		1300		// max t1l,t0h small width, rx;
`define	T_XR		1600		// center small/large, rx;
`define	TMIN_LR		2325		// min t1h,t0l large width, rx;
`define	TMAX_LR		63425		// max t1h,t0l large width, rx;
`define	TMAX_TE		25000		// max transfer temination signal;
`define	TMIN_RST	100000		// min reset low time;

	// behavioral model

	initial
	begin
		$display("%M: joy channel behavioral controller model");
		jctrl_mon = $test$plusargs("jctrl_mon");
	end

	// controller registers used by simulation;
	// collision have to be reenabled after use;

	reg enable;				// enable controller;
	reg master;				// behave as master;
	reg reset;				// drive JoyChannel 0 for reset testing;
	reg [3:0] div;			// configurable controller clock divider;
	reg [15:0] button;		// current button status;
	reg [7:0] x, y;			// current joystick counts;
	reg [7:0] type_l;		// type low;
	reg [7:0] type_h;		// type high;
	reg [7:0] status;		// status;
	reg rsp_echo;			// echo tx data for unsupported commands;
	reg rsp_random;			// randomize response timing;
	reg [3:0] collide;		// force collision in cmd state, [3] is enable;
	reg [5:0] framerr;		// force frame error at response bit, [5] is enable;
	reg glitch_detect;		// enable glitch detection;

	initial
	begin
		enable = 0;			// controller is disabled by default;
		master = 0;			// default is slave;
		reset = 0;			// default is off;
		div = 4'h9;			// divide by 10;
		x = 0;				// joy stick at 0,0;
		y = 0;
		button = 16'h0000;	// no button pressed;
		type_l = {
			1'b0,			// no extended command;
			4'b0000,		// reserved;
			1'b0,			// no joy port;
			2'b10 };		// absolute counter;
		type_h = {
			2'b00,			// no eeprom;
			1'b0,			// undefined;
			5'b00000 };		// device id is 0;
		status = {
			1'b0,			// eeprom not writing;
			4'b0000,		// reserved;
			1'b0,			// no joy port crc error;
			1'b0,			// joy port card not removed;
			1'b0 };			// joy port card not inserted;
		rsp_echo = 0;		// do not echo tx data for unsupported commands;
		rsp_random = 0;		// randomization off;
		collide = 4'h0;		// no collision;
		framerr = 6'd0;		// no frame error;
		glitch_detect = 1'b1;
	end

	// return random for response randomization;

	function [7:0] rsp_rand;
		input [7:0] min;
		begin
			rsp_rand = min + (rsp_random? ($random & 4'hf) : 0);
		end
	endfunction

	// print configuration changes;

	reg jbus_oe;		// jbus output enable;
	reg tx_on;			// transmitter on;

	always @(enable or master or reset or rsp_random or rsp_echo or collide or framerr or glitch_detect)
	begin
		if(jctrl_mon) begin
			$display("%t: %M: enable %b, master %b, reset %b, rsp random %b echo %b, collide %b, framerr %b, glitch %b",
				$time, enable, master, reset, rsp_random, rsp_echo, collide, framerr, glitch_detect);
		end
	end

	// run behavioral model at configurable clock;
	// base clock is 10MHz;

`define	BCLOCK_PERIOD	100

	reg bclock;			// base clock;

	initial
		bclock = 0;
	always
		#(`BCLOCK_PERIOD / 2) bclock = ~bclock;

	// divide clock down to simulation clock;
	// overwrite the div register for different config;

	reg [3:0] count;	// base clock counter;
	wire max_cnt;		// max count reached;
	reg clock;			// controller clock;

	initial
	begin
		count = 4'h0;		// start at 0;
		clock = 0;
	end

	assign max_cnt = (count == div);

	always @(posedge bclock)
	begin
		count <= max_cnt? 4'h0 : (count + 1);
		clock <= max_cnt;
	end

	// joy channel signal has pullup;

	initial
	begin
		jbus_oe = 0;		// tri-stated at reset;
	end

	pullup ( jbus );

	assign jbus = (jbus_oe | reset)? 1'b0 : 1'bz;

	// joy channel receiver;

	reg last;					// last joybus value;
	reg val;					// value before transition;
	integer ltime;				// last time jbus changed;
	integer ctime;				// current time;
	reg [9:0] state;
	reg [9:0] idlestate;		// defualt idle state;
	reg [9:0] newstate;			// controller state;
	wire state_rcv;				// in receive phase;
	wire [5:0] state_byte;		// byte state;
	wire [2:0] state_bit;		// bit state;
	reg [2:0] rx_bit;			// current rx bit;
	reg [7:0] rx_byte;			// received byte;
	reg [7:0] rx_last;			// last receive byte index;
	reg rx_reflect;				// reflect received bytes;
	reg [7:0] rx_data [0:35];	// command/data bytes;
	reg [1:0] pulse;			// pulse states;
	reg [7:0] rx_size;			// receive size, 0 none;
	reg [7:0] tx_size;			// transmit size, 0 none;
	reg [7:0] tx_data [0:35];	// transmit bytes;
	reg [7:0] rdata [0:35];		// data bytes;
	reg [7:0] crc;				// crc value, really checksum;
	integer n;

	// state encodings;
	// CTRL_RCVX: [9] is rcv phase, [8:3] are byte index, [2:0] are bit index;

	assign state_rcv = state[9];
	assign state_byte = state[8:3];
	assign state_bit = state[2:0];

`define	CTRL_RESET	'b0000000000		// controller in reset;
`define	CTRL_SIDLE	'b0000000001		// slave idle state;
`define	CTRL_TERM	'b0000000010		// transfer temination;
`define	CTRL_XMIT	'b0000000011		// transmit state;
`define	CTRL_SEP	'b0000000100		// wait for transfer separator;
`define	CTRL_MIDLE	'b0000000101		// master idle state;
`define	CTRL_RCVX	'b1xxxxxxxxx		// receive cmd/data bits;
`define	CTRL_CMD0	'b1000000000		// receive cmd bit 0;
`define	CTRL_CMD7	'b1000000111		// receive cmd bit 7;
`define	CTRL_RSP0	'b1000001000		// receive rsp bit 0;

	initial
	begin
		idlestate = `CTRL_SIDLE;
		last = 1;
		ltime = 0;
		tx_size = 0;
		tx_on = 0;
	end

	// enable controller;

	always @(enable)
	begin
		if(enable == 0) begin
			tx_on = 0;
			jbus_oe = 0;
		end
		idlestate = master? `CTRL_XMIT : `CTRL_SIDLE;
		state = idlestate;
	end

	// set rx_data to x;

	task rx_data_x;
		integer n;
		begin
			for(n = 0; n < 35; n = n + 1)
				rx_data[n] = 'bx;
		end
	endtask

	// detect jbus level changes;
	// assert reset to stop controller if x,z or glitches are detected;

	always @(jbus)
	begin

		// capture current value and duration;

		val = jbus;
		ctime = $time - ltime;
		ltime = $time;
		last = val;

		// check for glitches;

		if(enable & (state != `CTRL_RESET)) begin
			if((val === 1'bx) | (val === 1'bz)) begin
				$display("ERROR: %t: %M: unexpected jbus %b last %b", $time, val, last);
				state = `CTRL_SEP;
			end
			if(glitch_detect & (ctime < `TMAX_GLITCH)) begin
				$display("ERROR: %t: %M: jbus %0dns glitch", $time, ctime);
				state = `CTRL_SEP;
			end
		end

		// controller state machine;

		casex(state)

			// joychannel reset;
			// wait for jbus to go H;

			`CTRL_RESET: begin
				if(jctrl_mon)
					$display("%t: %M: jbus %b while in reset", $time, val);
				if((val == 1) & (ctime >= `TMIN_RST)) begin
					if(jctrl_mon)
						$display("%t: %M: end of jbus reset", $time);
					state = idlestate;
				end
			end

			// slave idle state;
			// begin of new command, at negedge of jbus;

			`CTRL_SIDLE: begin
				if(enable & (val == 0)) begin
					if(ctime < `TMIN_TS)
						$display("ERROR: %t: %M: tS violation: %0dns", $time, ctime);
					if(jctrl_mon)
						$display("%t: %M: start of command", $time);
					state = `CTRL_CMD0;
					rx_last = 0;
					rx_data_x;
				end
			end

			// master idle state;
			// begin of response at negedge of jbus;
			// skip cmd byte state;

			`CTRL_MIDLE: begin
				if(enable & (val == 0)) begin
					if(ctime > `TMAX_TC)
						$display("ERROR: %t: %M: tC violation: %0dns", $time, ctime);
					if(jctrl_mon)
						$display("%t: %M: start of response", $time);
					state = `CTRL_RSP0;
					rx_size = 'bx;
					rx_data_x;
				end
			end

			// receive cmd/data bytes;
			// check pusle widths for bit timing;
			// go idle (drop command) when separator signal is seen;
			// reset if low time is longer than max large pulse width;

			`CTRL_RCVX: begin
				if(state == `CTRL_CMD0) begin
					rx_reflect = 0;
					rx_last = 0;
				end
				if(ctime < `TMAX_SR)
					pulse[val] = 0;
				else if(ctime < `T_XR) begin
					pulse[val] = 0;
					$display("ERROR: %t: %M: t1l/t0h violation: %0dns", $time, ctime);
				end else if(ctime < `TMIN_LR) begin
					pulse[val] = 1;
					$display("ERROR: %t: %M: t1h/t0l violation: %0dns", $time, ctime);
				end else if(ctime < `TMAX_LR)
					pulse[val] = 1;
				else if(val == 1) begin
					if(jctrl_mon) begin
						$display("%t: %M: transfer separator during command: %0dns",
							$time, ctime);
						$display("%t: %M: ignoring command", $time);
					end
					state = idlestate;
				end else begin
					$display("ERROR: %t: %M: start of jbus reset during command: %0dns",
						$time, ctime);
					state = `CTRL_RESET;
				end

				// set bit in received byte;
				// joy channel is msb-first;
				// wait for separator if bit timing has been violated;
				// shift in cmd bit on falling edge of jbus;

				if((val == 0) & state_rcv) begin
					rx_bit = state_bit ^ 3'b111;
					if(pulse == 2'b10) begin
						rx_byte[rx_bit] = 1'b0;
						newstate = state + 1;
					end else if(pulse == 2'b01) begin
						rx_byte[rx_bit] = 1'b1;
						newstate = state + 1;
					end else begin
						$display("ERROR: %t: %M: bit signal timing violation: %b",
							$time, pulse);
						rx_byte[rx_bit] = 1'bx;
						newstate = `CTRL_SEP;
					end
					if(state_bit == 'd7) begin
						rx_data[state_byte] = rx_byte;
						if(jctrl_mon)
							$display("%t: %M: received byte[%0d] 0x%h", $time, state_byte, rx_byte);
					end

					// interpret command byte;
					// command byte determines how many more bytes follow;

					if(state == `CTRL_CMD7) begin
						if(jctrl_mon)
							$display("%t: %M: received command %0d", $time, rx_data[0]);
						case(rx_byte)
							`JCTRL_STATUS,
							`JCTRL_RESET: rx_last = 0;
							`JCTRL_QUERY: rx_last = 0;
							`JCTRL_READ: rx_last = 2;
							`JCTRL_WRITE: rx_last = 34;
							default: begin
								if(rsp_echo)
									rx_last = (rx_byte[1:0] + 1);
								else begin
									rx_last = 0;
									$display("ERROR: %t: %M: cmd %0d not supported", $time, rx_data[0]);
								end
							end
						endcase
					end

					// end of receive;
					// now we can build the response;

					if(state == { 1'b1, rx_last[5:0], 3'd7 }) begin
						newstate = `CTRL_TERM;
						case(rx_data[0])
							`JCTRL_STATUS,
							`JCTRL_RESET: begin
								tx_size = 3;
								tx_data[0] = type_l;
								tx_data[1] = type_h;
								tx_data[2] = status;
							end
							`JCTRL_QUERY: begin
								tx_size = 4;
								tx_data[0] = button[7:0];
								tx_data[1] = button[15:8];
								tx_data[2] = x;
								tx_data[3] = y;
							end
							// return content of rdata buffer;
							`JCTRL_READ: begin
								tx_size = 33;
								crc = 0;
								for(n = 0; n < 32; n = n + 1) begin
									crc = crc + rdata[n];
									tx_data[n] = rdata[n];
								end
								rdata[32] = crc;
								tx_data[32] = crc;
							end
							// return checksum over data;
							// copy write data into rdata;
							`JCTRL_WRITE: begin
								tx_size = 1;
								crc = 0;
								for(n = 0; n < 32; n = n + 1) begin
									rdata[n] = rx_data[n + 3];
									crc = crc + rx_data[n + 3];
								end
								rdata[32] = crc;
								tx_data[0] = crc;
							end
							default: begin
								tx_size = 0;
								if(rsp_echo) begin
									tx_size = (rx_data[0] & 3) + 1;
									tx_data[0] = rx_data[1];
									tx_data[1] = rx_data[2];
									tx_data[2] = rx_data[3];
									tx_data[3] = rx_data[4];
									$display("%t: %M: echoing cmd %0d, %0d bytes", $time, rx_data[0], tx_size);
								end
							end
						endcase
					end
					state = newstate;
				end
			end

			// check low time for transfer termination signal;
			// falling edge of tE has been seen;
			// as slave, turn around to transmit after rising edge;

			`CTRL_TERM: begin
				if(ctime > `TMAX_TE) begin
					$display("ERROR: %t: %M: start of jbus reset instead of termination: %0dns",
						$time, ctime);
					state = `CTRL_RESET;
				end else begin
					state = `CTRL_XMIT;
					rx_size = rx_last + 1;
					tx_on = ~master & (tx_size > 0);
				end
			end

			// master has released jbus, pullups drive high;
			// turn to transmit to send response;

			`CTRL_XMIT: ;

			// wait for transfer separator;
			// after totally bogus timing on jbus;

			`CTRL_SEP: begin
				if((val == 0) && (ctime > `TMIN_TS)) begin
					if(jctrl_mon)
						$display("%t: %M: resynced to transfer separator", $time);
					state = `CTRL_CMD0;
				end
			end

			// should not get here;

			default: begin
				$display("ERROR: %t: %M: illegal state, reseting", $time);
				state = `CTRL_RESET;
			end
		endcase
	end

	// transmitter;
	// send command or response to command;
	// allows transmitter to be turned off anytime,
	// which is usefull for transmit error testing;

	integer tX, tE;			// random time in clocks;
	integer nb;				// byte index;
	reg [7:0] tx_byte;		// byte being sent;
	reg tx_bit;				// transmit bit;
	integer b;				// bit index;
	reg corrupt;			// cause frame error;

	always @(posedge tx_on)
	begin
		// generate random tC before sending;
		// guarantee minimum of one clock;

		tX = rsp_rand(2);
		repeat(tX) @(posedge clock);

		// transmit all bytes, msb first;
		// randomize H time as well;

		for(nb = 0; enable && (nb < tx_size); nb = nb + 1) begin
			tx_byte = tx_data[nb];
			if(jctrl_mon)
				$display("%t: %M: sending byte[%0d] 0x%h", $time, nb, tx_byte);
			for(b = 7; enable && (b >= 0); b = b - 1) begin
				corrupt = framerr[5] & ({nb[1:0], b[2:0]} == framerr[4:0]);
				tx_bit = tx_byte[b];
				if(tx_bit === 1'bx) begin
					$display("ERROR: %t: %M: tx_bit %b", $time, tx_bit);
					jbus_oe = 1'bx;
				end else
					jbus_oe = 1;
				tX = rsp_rand(0);
				if((tx_bit == 0) & (tX > 0) & !corrupt) begin
					repeat(tX) @(posedge clock);
				end
				@(posedge clock);		// start bit;
				if((tx_bit == 1) & !corrupt)
					jbus_oe = 0;		// 1 bit;
				@(posedge clock);
				if(corrupt) begin
					jbus_oe = 0;		// cause frame error;
					if(jctrl_mon)
						$display("%t: %M: forcing frame error", $time);
					framerr = 'd0;
				end
				@(posedge clock);
				if((tx_bit == 0) & !corrupt)
					jbus_oe = 0;		// 0 bit;
				@(posedge clock);
				tX = rsp_rand(0);
				if((tx_bit == 1) & (tX > 0) & !corrupt) begin
					repeat(tX) @(posedge clock);
				end
			end
		end

		// send transfer termination signal;
		// randomize tE time;

		if(enable) begin
			jbus_oe = 1;
			tE = rsp_rand(1);
			repeat(tE) @(posedge clock);
			jbus_oe = 0;
			@(posedge clock);
			if(jctrl_mon)
				$display("%t: %M: %0s sent", $time, master? "comand" : "response");
		end

		// turn off transmitter;

		jbus_oe = 0;
		tx_on = 0;
		if(master) begin
			rx_size = 'bx;
			state = `CTRL_MIDLE;
		end else
			state = `CTRL_SIDLE;
	end

	// force collision during command phase;
	// needed for error testing of si joy channel controllers;
	// clear collide flag;

	integer ncc;			// # of collision clocks;

	always @(posedge clock)
	begin
		if(collide[3] & state_rcv & (collide[2:0] == state_bit)) begin
			collide = 'h0;
			ncc = 4 + ($random() & 'hf);
			if(jctrl_mon)
				$display("%t: %M: forcing collision for %0d clocks", $time, ncc);
			repeat(ncc) begin
				jbus_oe = 1;
				@(posedge clock);
			end
			jbus_oe = 0;
			state = idlestate;
		end
	end

endmodule