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mt46v4m32_tsop.v 49.1 KB
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/****************************************************************************************
*
*    File Name:  MT46V4M32_TSOP.V  
*      Version:  2.1
*         Date:  March 19th, 2002
*        Model:  BUS Functional
*    Simulator:  Aldec, ModemSim, NCDesktop
*
* Dependencies:  None
*
*       Author:  Son P. Huynh
*        Email:  sphuynh@micron.com
*        Phone:  (208) 368-3825
*      Company:  Micron Technology, Inc.
*  Part Number:  MT46V4M32 TSOP Package (1Meg x 32 x 4 Banks)
*
*  Description:  Micron 128Mb SDRAM DDR (Double Data Rate)
*
*   Limitation:  - Doesn't check for 8K-cycle refresh
*
*         Note:  - Set simulator resolution to "ps" accuracy
*                - Set Debug = 0 to disable $display messages
*                - Model assume Clk and Clk# crossing at both edge
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright  1998 Micron Semiconductor Products, Inc.
*                All rights researved
*
* Rev  Author          Phone         Date        Changes
* ---  --------------  ------------  ----------  ---------------------------------------
* 2.1  Son Huynh       208-368-3825  03/19/2002  - Second Release
*      Micron Technology Inc.                    - Fix tWR and several incompatability
*                                                  between different simulators
*
****************************************************************************************/

// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 1ps

module mt46v4m32_tsop (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);

    // Timing Parameters for -5 (CL = 2)
    parameter tCK       =       5.0;
    parameter tMRD      =       2.0;    // 2 tCK
    parameter tRAS      =      40.0;
    parameter tRC       =      60.0;
    parameter tRFC      =      60.0;
    parameter tRCDR     =      20.0;
    parameter tRCDW     =      10.0;
    parameter tRP       =      20.0;
    parameter tRRD      =       2.0;    // 2 tCK
    parameter tWR       =       2.0;    // 2 tCK

    // Constant Parameters
    parameter addr_bits =      12;
    parameter data_bits =      32;
    parameter cols_bits =       8;
    parameter mem_sizes = 1048575;

    // Port Declarations
    inout     [data_bits - 1 : 0] Dq;
    inout                 [3 : 0] Dqs;
    input     [addr_bits - 1 : 0] Addr;
    input                 [1 : 0] Ba;
    input                         Clk;
    input                         Clk_n;
    input                         Cke;
    input                         Cs_n;
    input                         Ras_n;
    input                         Cas_n;
    input                         We_n;
    input                 [3 : 0] Dm;

    // Data pair
    reg                   [3 : 0] Dm_temp;
    reg                   [7 : 0] Dm_pair;
    reg                  [31 : 0] Dq_temp;
    reg                  [63 : 0] Dq_pair;
    
    // Mode Register
    reg       [addr_bits - 1 : 0] Mode_reg;

    // Internal System Clock
    reg                           CkeZ, Sys_clk;

    // Internal Dqs initialize
    reg                           Dqs_int;

    // Dqs buffer
    reg                   [3 : 0] Dqs_out;

    // Dq buffer
    reg       [data_bits - 1 : 0] Dq_out, Dq_buf;

    // Read pipeline variables
    reg                           Read_cmnd [0 : 8];
    reg                   [1 : 0] Read_bank [0 : 8];
    reg       [cols_bits - 1 : 0] Read_cols [0 : 8];

    // Write pipeline variables
    reg                           Write_cmnd [0 : 2];
    reg                   [1 : 0] Write_bank [0 : 2];
    reg       [cols_bits - 1 : 0] Write_cols [0 : 2];

    // Auto precharge variables
    reg                           Read_precharge  [0 : 3];
    reg                           Write_precharge [0 : 3];
    integer                       Count_precharge [0 : 3];

    // Manual precharge variables
    reg                           A8_precharge  [0 : 8];
    reg                   [1 : 0] Bank_precharge [0 : 8];
    reg                           Cmnd_precharge [0 : 8];

    // Burst terminate variables
    reg                           Cmnd_bst [0 : 8];

    // Memory Banks
    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes];

    // Burst counter
    reg       [cols_bits - 1 : 0] Burst_counter;

    // Burst Direction (only used in x32 part)
    reg                           Burst_dir;
    reg                           Burst_dir_pipe [0 : 8];

    // Precharge variables
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;

    // Activate variables
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;

    // Data IO variables
    reg                           Data_in_enable;
    reg                           Data_out_enable;

    // Internal address mux variables
    //reg       [cols_bits - 1 : 0] Col_brst;
    reg                   [1 : 0] Prev_bank;
    reg                   [1 : 0] Bank_addr;
    reg       [cols_bits - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
    reg       [addr_bits - 1 : 0] Rows_addr;
    reg       [addr_bits - 1 : 0] B0_row_addr;
    reg       [addr_bits - 1 : 0] B1_row_addr;
    reg       [addr_bits - 1 : 0] B2_row_addr;
    reg       [addr_bits - 1 : 0] B3_row_addr;

    // DLL Reset variable
    reg                           DLL_enable;
    reg                           DLL_reset;
    reg                           DLL_done;
    integer                       DLL_count;

    // Commands Decode
    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1];
    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;

    // Burst Length Decode
    wire      Burst_length_2  = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_4  = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
    wire      Burst_length_8  = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
    wire      Burst_length_f  =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];

    // CAS Latency Decode
    wire      Cas_latency_15  =  Mode_reg[6] & ~Mode_reg[5] &  Mode_reg[4];
    wire      Cas_latency_2   = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_25  =  Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
    wire      Cas_latency_3   = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
    wire      Cas_latency_4   =  Mode_reg[6] & ~Mode_reg[5] & ~Mode_reg[4];

    // DQS Buffer
    assign    Dqs = Dqs_out;

    // DQ Buffer
    assign    Dq  = Dq_out;

    // Debug message
    wire      Debug = 1'b0;

    // Timing Check
    integer   MRD_chk;
    time      RFC_chk;
    integer   RRD_chk;
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
    time      RC_chk0, RC_chk1, RC_chk2, RC_chk3;
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
    integer   WR_chk0, WR_chk1, WR_chk2, WR_chk3;

    initial begin
        CkeZ = 1'b0;
        Sys_clk = 1'b0;
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
        Dqs_int = 1'b0;
        Dqs_out = 4'bz;
        Dq_out = {data_bits{1'bz}};
        Data_in_enable = 1'b0;
        Data_out_enable = 1'b0;
        DLL_enable = 1'b0;
        DLL_reset = 1'b0;
        DLL_done = 1'b0;
        DLL_count = 0;
        MRD_chk = 0;
        RFC_chk = 0;
        RRD_chk = 0;
        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
        {RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
        {WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
    end

    // System Clock
    always begin
        @ (posedge Clk) begin
            Sys_clk = CkeZ;
            CkeZ = Cke;
        end
        @ (negedge Clk) begin
            Sys_clk = 1'b0;
        end
    end

    // Burst Decode
    task Burst_Decode;
    begin
        // Advance Burst Counter
        Burst_counter = Burst_counter + 1;

        // Burst Type
        if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst
            if (Burst_dir === 1'b0) begin                       // Forward Direction
                Cols_temp = Cols_addr + 1;
            end else begin                                      // Reverse Direction (x32 only)
                Cols_temp = Cols_addr - 1;
            end
        end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst
            Cols_temp[2] =  Burst_counter[2] ^  Cols_brst[2];
            Cols_temp[1] =  Burst_counter[1] ^  Cols_brst[1];
            Cols_temp[0] =  Burst_counter[0] ^  Cols_brst[0];
        end

        // Burst Length
        if (Burst_length_2 === 1'b1) begin                      // Burst Length = 2
            Cols_addr [0] = Cols_temp [0];
        end else if (Burst_length_4 === 1'b1) begin             // Burst Length = 4
            Cols_addr [1 : 0] = Cols_temp [1 : 0];
        end else if (Burst_length_8 === 1'b1) begin             // Burst Length = 8
            Cols_addr [2 : 0] = Cols_temp [2 : 0];
        end else begin                                          // Burst Length = FULL
            Cols_addr = Cols_temp;
        end

        // Data Counter
        if (Burst_length_2 === 1'b1) begin
            if (Burst_counter >= 2) begin
                if (Data_in_enable === 1'b1) begin
                    Data_in_enable = 1'b0;
                end else if (Data_out_enable === 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end else if (Burst_length_4 === 1'b1) begin
            if (Burst_counter >= 4) begin
                if (Data_in_enable === 1'b1) begin
                    Data_in_enable = 1'b0;
                end else if (Data_out_enable === 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end else if (Burst_length_8 === 1'b1) begin
            if (Burst_counter >= 8) begin
                if (Data_in_enable === 1'b1) begin
                    Data_in_enable = 1'b0;
                end else if (Data_out_enable === 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end
    end
    endtask

    // Manual Precharge Pipeline
    task Manual_Precharge_Pipeline;
    begin
        // A8 Precharge Pipeline
        A8_precharge[0] = A8_precharge[1];
        A8_precharge[1] = A8_precharge[2];
        A8_precharge[2] = A8_precharge[3];
        A8_precharge[3] = A8_precharge[4];
        A8_precharge[4] = A8_precharge[5];
        A8_precharge[5] = A8_precharge[6];
        A8_precharge[6] = A8_precharge[7];
        A8_precharge[7] = A8_precharge[8];
        A8_precharge[8] = 1'b0;

        // Bank Precharge Pipeline
        Bank_precharge[0] = Bank_precharge[1];
        Bank_precharge[1] = Bank_precharge[2];
        Bank_precharge[2] = Bank_precharge[3];
        Bank_precharge[3] = Bank_precharge[4];
        Bank_precharge[4] = Bank_precharge[5];
        Bank_precharge[5] = Bank_precharge[6];
        Bank_precharge[6] = Bank_precharge[7];
        Bank_precharge[7] = Bank_precharge[8];
        Bank_precharge[8] = 2'b0;

        // Command Precharge Pipeline
        Cmnd_precharge[0] = Cmnd_precharge[1];
        Cmnd_precharge[1] = Cmnd_precharge[2];
        Cmnd_precharge[2] = Cmnd_precharge[3];
        Cmnd_precharge[3] = Cmnd_precharge[4];
        Cmnd_precharge[4] = Cmnd_precharge[5];
        Cmnd_precharge[5] = Cmnd_precharge[6];
        Cmnd_precharge[6] = Cmnd_precharge[7];
        Cmnd_precharge[7] = Cmnd_precharge[8];
        Cmnd_precharge[8] = 1'b0;

        // Terminate a Read if same bank or all banks
        if (Cmnd_precharge[0] === 1'b1) begin
            if (Bank_precharge[0] === Bank_addr || A8_precharge[0] === 1'b1) begin
                if (Data_out_enable === 1'b1) begin
                    Data_out_enable = 1'b0;
                end
            end
        end
    end
    endtask

    // Burst Terminate Pipeline
    task Burst_Terminate_Pipeline;
    begin
        // Command Precharge Pipeline
        Cmnd_bst[0] = Cmnd_bst[1];
        Cmnd_bst[1] = Cmnd_bst[2];
        Cmnd_bst[2] = Cmnd_bst[3];
        Cmnd_bst[3] = Cmnd_bst[4];
        Cmnd_bst[4] = Cmnd_bst[5];
        Cmnd_bst[5] = Cmnd_bst[6];
        Cmnd_bst[6] = Cmnd_bst[7];
        Cmnd_bst[7] = Cmnd_bst[8];
        Cmnd_bst[8] = 1'b0;

        // Terminate a Read regardless of banks
        if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
            Data_out_enable = 1'b0;
        end
    end
    endtask

    // Burst Direction Pipeline (x32 only)
    task Burst_Direction_Pipeline;
    begin
        // read command pipeline
        Burst_dir_pipe [0] = Burst_dir_pipe [1];
        Burst_dir_pipe [1] = Burst_dir_pipe [2];
        Burst_dir_pipe [2] = Burst_dir_pipe [3];
        Burst_dir_pipe [3] = Burst_dir_pipe [4];
        Burst_dir_pipe [4] = Burst_dir_pipe [5];
        Burst_dir_pipe [5] = Burst_dir_pipe [6];
        Burst_dir_pipe [6] = Burst_dir_pipe [7];
        Burst_dir_pipe [7] = Burst_dir_pipe [8];
        Burst_dir_pipe [8] = 1'b0;
    end
    endtask

    // Dq and Dqs Drivers
    task Dq_Dqs_Drivers;
    begin
        // read command pipeline
        Read_cmnd [0] = Read_cmnd [1];
        Read_cmnd [1] = Read_cmnd [2];
        Read_cmnd [2] = Read_cmnd [3];
        Read_cmnd [3] = Read_cmnd [4];
        Read_cmnd [4] = Read_cmnd [5];
        Read_cmnd [5] = Read_cmnd [6];
        Read_cmnd [6] = Read_cmnd [7];
        Read_cmnd [7] = Read_cmnd [8];
        Read_cmnd [8] = 1'b0;

        // read bank pipeline
        Read_bank [0] = Read_bank [1];
        Read_bank [1] = Read_bank [2];
        Read_bank [2] = Read_bank [3];
        Read_bank [3] = Read_bank [4];
        Read_bank [4] = Read_bank [5];
        Read_bank [5] = Read_bank [6];
        Read_bank [6] = Read_bank [7];
        Read_bank [7] = Read_bank [8];
        Read_bank [8] = 2'b0;

        // read column pipeline
        Read_cols [0] = Read_cols [1];
        Read_cols [1] = Read_cols [2];
        Read_cols [2] = Read_cols [3];
        Read_cols [3] = Read_cols [4];
        Read_cols [4] = Read_cols [5];
        Read_cols [5] = Read_cols [6];
        Read_cols [6] = Read_cols [7];
        Read_cols [7] = Read_cols [8];
        Read_cols [8] = 0;

        // Initialize Read command
        if (Read_cmnd [0] === 1'b1) begin
            Data_out_enable = 1'b1;
            Bank_addr = Read_bank [0];
            Cols_addr = Read_cols [0];
            Cols_brst = Cols_addr [2 : 0];
            Burst_counter = 0;
            Burst_dir = Burst_dir_pipe [0];

            // Row Address Mux
            case (Bank_addr)
                2'd0    : Rows_addr = B0_row_addr;
                2'd1    : Rows_addr = B1_row_addr;
                2'd2    : Rows_addr = B2_row_addr;
                2'd3    : Rows_addr = B3_row_addr;
                default : $display ("At time %t ERROR: Invalid Bank Address", $time);
            endcase
        end

        // Toggle Dqs during Read command
        if (Data_out_enable === 1'b1) begin
            Dqs_int = 1'b0;
            if (Dqs_out === 4'b0000) begin
                Dqs_out = 4'b1111;
            end else if (Dqs_out === 4'b1111) begin
                Dqs_out = 4'b0000;
            end else begin
                Dqs_out = 4'b0000;
            end
        end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
            Dqs_out = 4'bzzzz;
        end

        // Initialize dqs for Read command
        if (Read_cmnd [2] === 1'b1) begin
            if (Data_out_enable === 1'b0) begin
                Dqs_int = 1'b1;
                Dqs_out = 4'b0000;
            end
        end

        // Read latch
        if (Data_out_enable === 1'b1) begin
            // output data
            case (Bank_addr)
                2'd0    : Dq_out = Bank0 [{Rows_addr, Cols_addr}];
                2'd1    : Dq_out = Bank1 [{Rows_addr, Cols_addr}];
                2'd2    : Dq_out = Bank2 [{Rows_addr, Cols_addr}];
                2'd3    : Dq_out = Bank3 [{Rows_addr, Cols_addr}];
                default : $display ("At time %t ERROR: Invalid Bank Address", $time);
            endcase

            // Increase burst counter
            Burst_Decode;
        end else begin
            Dq_out = {data_bits{1'bz}};
        end
    end
    endtask

    // Write FIFO and DM Mask Logic
    task Write_FIFO_DM_Mask_Logic;
    begin
        // Write command pipeline
        Write_cmnd [0] = Write_cmnd [1];
        Write_cmnd [1] = Write_cmnd [2];
        Write_cmnd [2] = 1'b0;

        // Write command pipeline
        Write_bank [0] = Write_bank [1];
        Write_bank [1] = Write_bank [2];
        Write_bank [2] = 2'b0;

        // Write column pipeline
        Write_cols [0] = Write_cols [1];
        Write_cols [1] = Write_cols [2];
        Write_cols [2] = {cols_bits{1'b0}};

        // Initialize Write command
        if (Write_cmnd [0] === 1'b1) begin
            Data_in_enable = 1'b1;
            Bank_addr = Write_bank [0];
            Cols_addr = Write_cols [0];
            Cols_brst = Cols_addr [2 : 0];
            Burst_counter = 0;
            Burst_dir = Burst_dir_pipe [0];

            // Row address mux
            case (Bank_addr)
                2'd0    : Rows_addr = B0_row_addr;
                2'd1    : Rows_addr = B1_row_addr;
                2'd2    : Rows_addr = B2_row_addr;
                2'd3    : Rows_addr = B3_row_addr;
                default : $display ("At time %t ERROR: Invalid Row Address", $time);
            endcase
        end

        // Write data
        if (Data_in_enable === 1'b1) begin
            // Write first data
            if (Dm_pair [0] === 1'b0 || Dm_pair [1] === 1'b0 || Dm_pair [2] === 1'b0 || Dm_pair [3] === 1'b0) begin
                // Data Buffer
                case (Bank_addr)
                    2'd0    : Dq_buf = Bank0 [{Rows_addr, Cols_addr}];
                    2'd1    : Dq_buf = Bank1 [{Rows_addr, Cols_addr}];
                    2'd2    : Dq_buf = Bank2 [{Rows_addr, Cols_addr}];
                    2'd3    : Dq_buf = Bank3 [{Rows_addr, Cols_addr}];
                    default : $display ("At time %t ERROR: Invalid Bank Address", $time);
                endcase

                // Data mask
                if (Dm_pair [0] === 1'b0) begin
                    Dq_buf [7 : 0] = Dq_pair [7 : 0];
                end

                if (Dm_pair [1] === 1'b0) begin
                    Dq_buf [15 : 8] = Dq_pair [15 : 8];
                end

                if (Dm_pair [2] === 1'b0) begin
                    Dq_buf [23 : 16] = Dq_pair [23 : 16];
                end

                if (Dm_pair [3] === 1'b0) begin
                    Dq_buf [31 : 24] = Dq_pair [31 : 24];
                end

                // Write Data
                case (Bank_addr)
                    2'd0    : Bank0 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd1    : Bank1 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd2    : Bank2 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd3    : Bank3 [{Rows_addr, Cols_addr}] = Dq_buf;
                    default : $display ("At time %t ERROR: Invalid Bank Address", $time);
                endcase
            end

            //  Increase Burst Counter
            Burst_Decode;

            // Write second data
            if (Dm_pair [4] === 1'b0 || Dm_pair [5] === 1'b0 || Dm_pair [6] === 1'b0 || Dm_pair [7] === 1'b0) begin
                // Data Buffer
                case (Bank_addr)
                    2'd0    : Dq_buf = Bank0 [{Rows_addr, Cols_addr}];
                    2'd1    : Dq_buf = Bank1 [{Rows_addr, Cols_addr}];
                    2'd2    : Dq_buf = Bank2 [{Rows_addr, Cols_addr}];
                    2'd3    : Dq_buf = Bank3 [{Rows_addr, Cols_addr}];
                    default : $display ("At time %t ERROR: Invalid Bank Address", $time);
                endcase

                // Data mask
                if (Dm_pair [4] === 1'b0) begin
                    Dq_buf [7 : 0] = Dq_pair [39 : 32];
                end

                if (Dm_pair [5] === 1'b0) begin
                    Dq_buf [15 : 8] = Dq_pair [47 : 40];
                end

                if (Dm_pair [6] === 1'b0) begin
                    Dq_buf [23 : 16] = Dq_pair [55 : 48];
                end

                if (Dm_pair [7] === 1'b0) begin
                    Dq_buf [31 : 24] = Dq_pair [63 : 56];
                end

                // Write Data
                case (Bank_addr)
                    2'd0    : Bank0 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd1    : Bank1 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd2    : Bank2 [{Rows_addr, Cols_addr}] = Dq_buf;
                    2'd3    : Bank3 [{Rows_addr, Cols_addr}] = Dq_buf;
                    default : $display ("At time %t ERROR: Invalid Bank Address", $time);
                endcase
            end
            
            // Increase Burst Counter
            Burst_Decode;

            // tWR start and tWTR check
            if (Dm_pair [0] === 1'b0 || Dm_pair [1] === 1'b0 || Dm_pair [2] === 1'b0 || Dm_pair [3] === 1'b0 ||
                Dm_pair [4] === 1'b0 || Dm_pair [5] === 1'b0 || Dm_pair [6] === 1'b0 || Dm_pair [7] === 1'b0)  begin
                case (Bank_addr)
                    2'd0    : WR_chk0 = 0;
                    2'd1    : WR_chk1 = 0;
                    2'd2    : WR_chk2 = 0;
                    2'd3    : WR_chk3 = 0;
                    default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
                endcase

                // tWTR check
                if (Read_enable === 1'b1 && Bank_addr === Ba) begin
                    $display ("At time %t ERROR: tWTR violation during Read", $time);
                end
            end
        end
    end
    endtask

    // Auto Precharge Calculation
    task Auto_Precharge_Calculation;
    begin
        // Precharge counter
        if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
            Count_precharge [0] = Count_precharge [0] + 1;
        end
        if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
            Count_precharge [1] = Count_precharge [1] + 1;
        end
        if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
            Count_precharge [2] = Count_precharge [2] + 1;
        end
        if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
            Count_precharge [3] = Count_precharge [3] + 1;
        end

        // Read with AutoPrecharge Calculation
        //      The device start internal precharge when:
        //          1.  Meet tRAS requirement
        //          2.  BL/2 cycles after command
        if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge[0] >= 1)  ||
                (Burst_length_4 === 1'b1 && Count_precharge[0] >= 2)  ||
                (Burst_length_8 === 1'b1 && Count_precharge[0] >= 4)) begin
                Pc_b0 = 1'b1;
                Act_b0 = 1'b0;
                RP_chk0 = $time;
                Read_precharge[0] = 1'b0;
            end
        end
        if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge[1] >= 1)  ||
                (Burst_length_4 === 1'b1 && Count_precharge[1] >= 2)  ||
                (Burst_length_8 === 1'b1 && Count_precharge[1] >= 4)) begin
                Pc_b1 = 1'b1;
                Act_b1 = 1'b0;
                RP_chk1 = $time;
                Read_precharge[1] = 1'b0;
            end
        end
        if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge[2] >= 1)  ||
                (Burst_length_4 === 1'b1 && Count_precharge[2] >= 2)  ||
                (Burst_length_8 === 1'b1 && Count_precharge[2] >= 4)) begin
                Pc_b2 = 1'b1;
                Act_b2 = 1'b0;
                RP_chk2 = $time;
                Read_precharge[2] = 1'b0;
            end
        end
        if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge[3] >= 1)  ||
                (Burst_length_4 === 1'b1 && Count_precharge[3] >= 2)  ||
                (Burst_length_8 === 1'b1 && Count_precharge[3] >= 4)) begin
                Pc_b3 = 1'b1;
                Act_b3 = 1'b0;
                RP_chk3 = $time;
                Read_precharge[3] = 1'b0;
            end
        end

        // Write with AutoPrecharge Calculation
        //      The device start internal precharge when:
        //          1.  Meet tRAS requirement
        //          2.  Two clock after last burst
        if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge [0] >= 4) ||
                (Burst_length_4 === 1'b1 && Count_precharge [0] >= 5) ||
                (Burst_length_8 === 1'b1 && Count_precharge [0] >= 7)) begin
                Pc_b0 = 1'b1;
                Act_b0 = 1'b0;
                RP_chk0 = $time;
                Write_precharge[0] = 1'b0;
            end
        end
        if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge [1] >= 4) ||
                (Burst_length_4 === 1'b1 && Count_precharge [1] >= 5) ||
                (Burst_length_8 === 1'b1 && Count_precharge [1] >= 7)) begin
                Pc_b1 = 1'b1;
                Act_b1 = 1'b0;
                RP_chk1 = $time;
                Write_precharge[1] = 1'b0;
            end
        end
        if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge [2] >= 4) ||
                (Burst_length_4 === 1'b1 && Count_precharge [2] >= 5) ||
                (Burst_length_8 === 1'b1 && Count_precharge [2] >= 7)) begin
                Pc_b2 = 1'b1;
                Act_b2 = 1'b0;
                RP_chk2 = $time;
                Write_precharge[2] = 1'b0;
            end
        end
        if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
            if ((Burst_length_2 === 1'b1 && Count_precharge [3] >= 4) ||
                (Burst_length_4 === 1'b1 && Count_precharge [3] >= 5) ||
                (Burst_length_8 === 1'b1 && Count_precharge [3] >= 7)) begin
                Pc_b3 = 1'b1;
                Act_b3 = 1'b0;
                RP_chk3 = $time;
                Write_precharge[3] = 1'b0;
            end
        end
    end
    endtask

    // Timing Check Counter
    task Timing_Check_Counter;
    begin
        // tMRD Counter
        MRD_chk = MRD_chk + 1;

        // tRRD Counter
        RRD_chk = RRD_chk + 1;

        // tWR Counter
        WR_chk0 = WR_chk0 + 1;
        WR_chk1 = WR_chk0 + 1;
        WR_chk2 = WR_chk0 + 1;
        WR_chk3 = WR_chk0 + 1;
    end
    endtask

    // DLL Counter
    task DLL_Counter;
    begin
        if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
            DLL_count = DLL_count + 1;
            if (DLL_count >= 200) begin
                DLL_done = 1'b1;
            end
        end
    end
    endtask

    // Control Logic
    task Control_Logic;
    begin
        // Auto Refresh
        if (Aref_enable === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t AREF : Auto Refresh", $time);
            end
            
            // Auto Refresh to Auto Refresh
            if ($time - RFC_chk < tRFC) begin
                $display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
            end
            
            // Precharge to Auto Refresh
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
                $display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
            end
            
            // Precharge to Auto Refresh
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
                $display ("At time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
            end
            
            // Record Current tRFC time
            RFC_chk = $time;
        end
    
        // Extended Mode Register
        if (Ext_mode_enable === 1'b1) begin
            if (Debug) begin
                $display ("At time %t EMR  : Extended Mode Register", $time);
            end
            if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
                if (Addr[0] === 1'b0) begin
                    DLL_enable = 1'b1;
                    if (Debug) begin
                        $display ("At time %t EMR  : Enable DLL", $time);
                    end
                end else begin
                    DLL_enable = 1'b0;
                    if (Debug) begin
                        $display ("At time %t EMR  : Disable DLL", $time);
                    end
                end
            end else begin
                $display ("At time %t ERROR: all banks must be Precharge before Extended Mode Register", $time);
            end

            // Precharge to EMR
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
                $display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
            end

            // LMR/EMR to LMR/EMR
            if (MRD_chk < tMRD) begin
                $display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
            end

            // Record current tMRD time
            MRD_chk = 0;
        end
    
        // Load Mode Register
        if (Mode_reg_enable === 1'b1) begin
            if (Debug) begin
                $display ("At time %t LMR  : Load Mode Register", $time);
            end

            // Register Mode
            Mode_reg = Addr;

            // DLL Reset
            if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
                DLL_reset = 1'b1;
                DLL_done = 1'b0;
                DLL_count = 0;
            end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
                $display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
            end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
                $display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
            end

            // Precharge to LMR
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
                $display ("At time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
            end

            // Precharge to LMR
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
                $display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
            end

            // LMR/EMR to LMR/EMR
            if (MRD_chk < tMRD) begin
                $display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
            end

            // Burst Length
            if (~((Addr[2 : 0] ===  3'b001) ||
                (Addr[2 : 0] ===  3'b010) ||
                (Addr[2 : 0] ===  3'b011) ||
                (Addr[3 : 0] === 4'b0111))) begin
                $display ("At time %t ERROR: Burst Length not supported", $time);
            end

            // CAS Latency
            if (~((Addr[6 : 4] === 3'b010) ||
                (Addr[6 : 4] === 3'b011) ||
                (Addr[6 : 4] === 3'b100) ||
                (Addr[6 : 4] === 3'b110))) begin
                $display ("At time %t ERROR: CAS Latency not supported", $time);
            end

            // Record current tMRD time
            MRD_chk = 0;
        end

        // Activate Block
        if (Active_enable === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t ACT  : Bank = %d Row = %d", $time, Ba, Addr);
            end

            // Activate an open bank can corrupted.
            if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||
                (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin
                $display ("At time %t ERROR: Bank = %d is already activated - data can be corrupted", $time, Ba);
            end
            
            // Activate Bank 0
            if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
                // Activate to Activate (same bank)
                if ($time - RC_chk0 < tRC) begin
                    $display ("At time %t ERROR: tRC violation during Activate bank %d", $time, Ba);
                end

                // Precharge to Activate
                if ($time - RP_chk0 < tRP) begin
                    $display ("At time %t ERROR: tRP violation during Activate bank %d", $time, Ba);
                end

                // Record variables for checking violation
                Act_b0 = 1'b1;
                Pc_b0 = 1'b0;
                B0_row_addr = Addr;
                RC_chk0  = $time;
                RCD_chk0 = $time;
                RAS_chk0 = $time;
            end

            // Activate Bank 1
            if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
                // Activate to Activate (same bank)
                if ($time - RC_chk1 < tRC) begin
                    $display ("At time %t ERROR: tRC violation during Activate bank %d", $time, Ba);
                end

                // Precharge to Activate
                if ($time - RP_chk1 < tRP) begin
                    $display ("At time %t ERROR: tRP violation during Activate bank %d", $time, Ba);
                end

                // Record variables for checking violation
                Act_b1 = 1'b1;
                Pc_b1 = 1'b0;
                B1_row_addr = Addr;
                RC_chk1  = $time;
                RCD_chk1 = $time;
                RAS_chk1 = $time;
            end

            // Activate Bank 2
            if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
                // Activate to Activate (same bank)
                if ($time - RC_chk2 < tRC) begin
                    $display ("At time %t ERROR: tRC violation during Activate bank %d", $time, Ba);
                end

                // Precharge to Activate
                if ($time - RP_chk2 < tRP) begin
                    $display ("At time %t ERROR: tRP violation during Activate bank %d", $time, Ba);
                end

                // Record variables for checking violation
                Act_b2 = 1'b1;
                Pc_b2 = 1'b0;
                B2_row_addr = Addr;
                RC_chk2  = $time;
                RCD_chk2 = $time;
                RAS_chk2 = $time;
            end

            // Activate Bank 3
            if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
                // Activate to Activate (same bank)
                if ($time - RC_chk3 < tRC) begin
                    $display ("At time %t ERROR: tRC violation during Activate bank %d", $time, Ba);
                end

                // Precharge to Activate
                if ($time - RP_chk3 < tRP) begin
                    $display ("At time %t ERROR: tRP violation during Activate bank %d", $time, Ba);
                end

                // Record variables for checking violation
                Act_b3 = 1'b1;
                Pc_b3 = 1'b0;
                B3_row_addr = Addr;
                RC_chk3  = $time;
                RCD_chk3 = $time;
                RAS_chk3 = $time;
            end

            // Activate to Activate (different bank)
            if ((Prev_bank != Ba) && (RRD_chk < tRRD)) begin
                $display ("At time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
            end
            
            // AutoRefresh to Activate
            if ($time - RFC_chk < tRFC) begin
                $display ("At time %t ERROR: tRFC violation during Activate bank %d", $time, Ba);
            end

            // Record variable for checking violation
            RRD_chk = 0;
            Prev_bank = Ba;
        end
    
        // Precharge Block - consider NOP if bank already precharged or in process of precharging
        if (Prech_enable === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t PRE  : Addr[8] = %b, Bank = %b, ", $time, Addr[8], Ba);
            end

            // EMR or LMR to Precharge
            if (MRD_chk < tMRD) begin
                $display ("At time %t ERROR: tMRD violation during Precharge", $time);
            end

            // Precharge bank 0
            if ((Addr[8] === 1'b1 || (Addr[8] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
                Act_b0 = 1'b0;
                Pc_b0 = 1'b1;
                RP_chk0 = $time;
                
                // Activate to Precharge Bank
                if ($time - RAS_chk0 < tRAS) begin
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
                end
                
                // tWR violation check for Write
                if (WR_chk0 < tWR) begin
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
                end
            end

            // Precharge bank 1
            if ((Addr[8] === 1'b1 || (Addr[8] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
                Act_b1 = 1'b0;
                Pc_b1 = 1'b1;
                RP_chk1 = $time;

                // Activate to Precharge Bank 1
                if ($time - RAS_chk1 < tRAS) begin
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
                end
                
                // tWR violation check for Write
                if (WR_chk1 < tWR) begin
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
                end
            end

            // Precharge bank 2
            if ((Addr[8] === 1'b1 || (Addr[8] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
                Act_b2 = 1'b0;
                Pc_b2 = 1'b1;
                RP_chk2 = $time;
                
                // Activate to Precharge Bank 2
                if ($time - RAS_chk2 < tRAS) begin
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
                end
                
                // tWR violation check for Write
                if (WR_chk2 < tWR) begin
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
                end
            end

            // Precharge bank 3
            if ((Addr[8] === 1'b1 || (Addr[8] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
                Act_b3 = 1'b0;
                Pc_b3 = 1'b1;
                RP_chk3 = $time;
                
                // Activate to Precharge Bank 3
                if ($time - RAS_chk3 < tRAS) begin
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
                end
                
                // tWR violation check for Write
                if (WR_chk3 < tWR) begin
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
                end
            end

            // Pipeline for READ
            if (Cas_latency_15 === 1'b1) begin
                A8_precharge[3] = Addr[8];
                Bank_precharge[3] = Ba;
                Cmnd_precharge[3] = 1'b1;
            end else if (Cas_latency_2 === 1'b1) begin
                A8_precharge[4] = Addr[8];
                Bank_precharge[4] = Ba;
                Cmnd_precharge[4] = 1'b1;
            end else if (Cas_latency_25 === 1'b1) begin
                A8_precharge[5] = Addr[8];
                Bank_precharge[5] = Ba;
                Cmnd_precharge[5] = 1'b1;
            end else if (Cas_latency_3 === 1'b1) begin
                A8_precharge[6] = Addr[8];
                Bank_precharge[6] = Ba;
                Cmnd_precharge[6] = 1'b1;
            end else if (Cas_latency_4 === 1'b1) begin
                A8_precharge[8] = Addr[8];
                Bank_precharge[8] = Ba;
                Cmnd_precharge[8] = 1'b1;
            end
        end
    
        // Burst terminate
        if (Burst_term === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t BST  : Burst Terminate",$time);
            end

            // Burst Terminate Command Pipeline for Read
            if (Cas_latency_15 === 1'b1) begin
                Cmnd_bst [3] = 1'b1;
            end else if (Cas_latency_2 === 1'b1) begin
                Cmnd_bst [4] = 1'b1;
            end else if (Cas_latency_25 === 1'b1) begin
                Cmnd_bst [5] = 1'b1;
            end else if (Cas_latency_3 === 1'b1) begin
                Cmnd_bst [6] = 1'b1;
            end else if (Cas_latency_4 === 1'b1) begin
                Cmnd_bst [8] = 1'b1;
            end

            // Illegal to burst terminate a Write
            if (Data_in_enable === 1'b1) begin
                $display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
            end
            
            // Illegal to burst terminate a Read with Auto Precharge
            if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
                Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
                $display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
            end
        end
        
        // Read Command
        if (Read_enable === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t READ : Bank = %d Col = %d", $time, Ba, Addr [7 : 0]);
            end

            // CAS Latency pipeline
            if (Cas_latency_15 === 1'b1) begin
                Read_cmnd [3] = 1'b1;
                Read_bank [3] = Ba;
                Read_cols [3] = Addr [9 : 0];
                Burst_dir_pipe [3] = Burst_length_f & Addr [0];
            end else if (Cas_latency_2 === 1'b1) begin
                Read_cmnd [4] = 1'b1;
                Read_bank [4] = Ba;
                Read_cols [4] = Addr [9 : 0];
                Burst_dir_pipe [4] = Burst_length_f & Addr [0];
            end else if (Cas_latency_25 === 1'b1) begin
                Read_cmnd [5] = 1'b1;
                Read_bank [5] = Ba;
                Read_cols [5] = Addr [9 : 0];
                Burst_dir_pipe [5] = Burst_length_f & Addr [0];
            end else if (Cas_latency_3 === 1'b1) begin
                Read_cmnd [6] = 1'b1;
                Read_bank [6] = Ba;
                Read_cols [6] = Addr [9 : 0];
                Burst_dir_pipe [6] = Burst_length_f & Addr [0];
            end else if (Cas_latency_4 === 1'b1) begin
                Read_cmnd [8] = 1'b1;
                Read_bank [8] = Ba;
                Read_cols [8] = Addr [9 : 0];
                Burst_dir_pipe [8] = Burst_length_f & Addr [0];
            end

            // Terminate a Write
            if (Data_in_enable === 1'b1) begin
                Data_in_enable = 1'b0;
            end

            // Interrupt a Read with Auto Precharge (same bank only)
            if (Read_precharge [Ba] === 1'b1) begin
                $display ("At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $time);
            end

            // Activate to Read
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
                $display("At time %t ERROR: Bank is not Activated for Read", $time);
            end

            // Activate to Read
            if ((Ba === 2'b00 && $time - RCD_chk0 < tRCDR) ||
                (Ba === 2'b01 && $time - RCD_chk1 < tRCDR) ||
                (Ba === 2'b10 && $time - RCD_chk2 < tRCDR) ||
                (Ba === 2'b11 && $time - RCD_chk3 < tRCDR)) begin
                $display("At time %t ERROR: tRCD violation during Read", $time);
            end

            // Auto Precharge
            if (Addr[8] === 1'b1) begin
                Read_precharge [Ba]= 1'b1;
                Count_precharge [Ba]= 0;
            end

            // Check for DLL reset before Read
            if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
                $display ("At time %t ERROR: DLL Reset not complete", $time);
            end
        end

        // Write Command
        if (Write_enable === 1'b1) begin
            // Display Debug Message
            if (Debug) begin
                $display ("At time %t WRITE: Bank = %d Col = %d", $time, Ba, Addr [7 : 0]);
            end

            // Pipeline for Write
            Write_cmnd [2] = 1'b1;
            Write_bank [2] = Ba;
            Write_cols [2] = Addr [9 : 0];
            Burst_dir_pipe [2] = Burst_length_f & Addr [0];

            // Interrupt a Write with Auto Precharge (same bank only)
            if (Write_precharge [Ba] === 1'b1) begin
                $display ("At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $time);
            end

            // Activate to Write
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
                $display("At time %t ERROR: Bank is not Activated for Write", $time);
            end

            // Activate to Write
            if ((Ba === 2'b00 && $time - RCD_chk0 < tRCDW) ||
                (Ba === 2'b01 && $time - RCD_chk1 < tRCDW) ||
                (Ba === 2'b10 && $time - RCD_chk2 < tRCDW) ||
                (Ba === 2'b11 && $time - RCD_chk3 < tRCDW)) begin
                $display("At time %t ERROR: tRCD violation during Write to Bank %d", $time, Ba);
            end

            // Auto Precharge
            if (Addr[8] === 1'b1) begin
                Write_precharge [Ba]= 1'b1;
                Count_precharge [Ba]= 0;
            end
        end
    end
    endtask

    // Main Logic
    always @ (posedge Sys_clk) begin
        Manual_Precharge_Pipeline;
        Burst_Terminate_Pipeline;
        Burst_Direction_Pipeline;
        Dq_Dqs_Drivers;
        Write_FIFO_DM_Mask_Logic;
        Auto_Precharge_Calculation;
        Timing_Check_Counter;
        DLL_Counter;
        Control_Logic;
    end

    always @ (negedge Sys_clk) begin
        Manual_Precharge_Pipeline;
        Burst_Terminate_Pipeline;
        Burst_Direction_Pipeline;
        Dq_Dqs_Drivers;
    end

    // Dqs Receiver
    always @ (posedge Dqs) begin
        // Latch data at posedge Dqs
        Dq_temp = Dq;
        Dm_temp = Dm;
    end

    always @ (negedge Dqs[0]) begin
        // Latch data at negedge Dqs
        Dq_pair = {Dq, Dq_temp};
        Dm_pair = {Dm, Dm_temp};
    end

    // Timing Check for -7 (CAS Latency = 2)
    specify
        specparam
                    tCH =  3.375,       // 0.45 * tCK
                    tCL =  3.375,       // 0.45 * tCK
                    tDH =  0.500,
                    tDS =  0.500,
                    tIH =  0.900,
                    tIS =  0.900;
        $setuphold(posedge Clk,   Cke,   tIS, tIH);
        $setuphold(posedge Clk,   Cs_n,  tIS, tIH);
        $setuphold(posedge Clk,   Cas_n, tIS, tIH);
        $setuphold(posedge Clk,   Ras_n, tIS, tIH);
        $setuphold(posedge Clk,   We_n,  tIS, tIH);
        $setuphold(posedge Clk,   Addr,  tIS, tIH);
        $setuphold(posedge Clk,   Ba,    tIS, tIH);
    endspecify

endmodule