========================================================================
- Kit           : OPENCAD-CB12 V3.1.0
- Library       : verilog
- Technology    : common
- Condition     : common
- Version       : 1.03
- Date          : Tue Jun 4 14:59:20 JST 2002
- Creater       : A.Nabatake
========================================================================

#                      < block-name >   < size >      < sum > < version >
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- File        clockdriver/TBBUFCKX6.v        465        34594       4.00
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- File           verilog_udp/DLSFQB.v       2734        59604       3.01
- File      verilog_udp/DLSFQ_LSSD2.v       1532        40274       3.02
- File             verilog_udp/LSSD.v       1428        29319       3.02
- File         verilog_udp/udp2down.v        494        34310       3.00
- File           verilog_udp/udp2up.v        492        34099       3.00
- File          verilog_udp/udp_MUX.v        623        41423       3.00
- File         verilog_udp/udp_PECL.v       1044         1113       1.00
- File          verilog_udp/udp_RSQ.v       6579        65323       3.00
- File         verilog_udp/udp_RSQB.v       7124        19598       3.00