TDGTOR2BCLX2.v
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// VERSION:1.01 DATE:01/04/06 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDGTOR2BCLX2 ( N01, H01, H02 );
input H01;
input H02;
output N01;
reg _N01;
reg notifier;
// Dummy Buffer
buf ( _H01, H01 );
buf ( _H02, H02 );
not ( _H01B, _H01 );
// or ( _N01, _H01B, _H02 );
buf (N01, _N01);
always @ ( notifier ) begin
_N01=1'bx;
end
always @ ( _H02 ) begin
casez ( {_H01B,_H02} )
2'b?1 : _N01=1;
2'b?0 : begin
if ( $time !== 0 ) begin
if (_N01===1'bx) _N01=1'bx;
else _N01=_H01B;
end
else begin
_N01=_H01B;
end
end
2'b1x : begin
if (_N01===1'bx) _N01=1'bx;
else _N01=1;
end
2'b0x : begin
_N01=1'bx;
end
default : _N01=1'bx;
endcase
end
always @ ( _H01 ) begin
if ( $time !== 0 )
if (_H02 !== 1'b1 ) begin
$display("");
$display($time,,"<Warning> : %m");
$display("\t\tChanged H01 while H02 is low.");
$display("\t\tN01 contents set to X.\n");
_N01=1'bx;
end
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, posedge H02, DMY_SPC, notifier );
$setup ( negedge H01, posedge H02, DMY_SPC, notifier );
$setup ( posedge H01, negedge H02, DMY_SPC, notifier );
$setup ( negedge H01, negedge H02, DMY_SPC, notifier );
$hold ( posedge H02, posedge H01, DMY_SPC, notifier );
$hold ( posedge H02, negedge H01, DMY_SPC, notifier );
$hold ( negedge H02, posedge H01, DMY_SPC, notifier );
$hold ( negedge H02, negedge H01, DMY_SPC, notifier );
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine