TDBIAUSBNNFPO.v
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// VERSION:1.03 DATE:2001/12/11 OpenCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAUSBNNFPO ( N01, N02, N03, N04, N05, H01, H02, H03, H04, H05, H06 );
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
inout N01;
output N02;
output N03;
output N04;
output N05;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
not ( _H03N, _H03 );
and ( _G001, _H01, _H03N );
bufif1 ( _G002, _G001, _H02 );
bufif1 ( N01, _G002, _H02 );
buf ( _N01, N01 );
udp_PECL u1 ( _G003, _N01, _H04 );
not ( _H05N, _H05 );
or ( N02, _G003, _H05N );
or ( _N04, _N01, _H06 );
or ( _N05, _H04, _H06 );
buf ( N04, _N04 );
buf ( N05, _N05 );
nor ( N03, _N04, _N05 );
defparam u1.PECL_DLY = 40001;
wire flag_PECL = u1.flag_PECL;
specify
specparam DMY_SPC=1:1:1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( H04 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H04 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H04 *> N05 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N04 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N05 ) = ( DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N03 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N04 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine