TDBIAUSBNNLPOC_PECL.v
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// VERSION:1.00 DATE:2002/08/01 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAUSBNNLPOC_PECL ( OUT, A, B );
input A ;
input B ;
output OUT ;
reg _OUT ;
reg flag_PECL ;
event Wait ;
parameter PECL_DLY = 1;
buf ( _A, A );
buf ( _B, B );
buf ( OUT, _OUT );
always @ ( _A or _B ) fork
`ifdef INCA
#1 flag_PECL = 0;
`else
`ifdef VCS
#1 flag_PECL = 0;
`else
flag_PECL = 0;
`endif
`endif
casez ( {_A,_B} )
2'b01 ,
2'b10 :
begin
disable diff_wait;
#1 _OUT = _A;
end
default :
-> Wait;
endcase
join
always @ ( Wait ) begin : diff_wait
#PECL_DLY
if (_A !== ~_B )
begin
flag_PECL = 1;
_OUT = 1'bx;
#1 flag_PECL = 0;
if ( _A === ~_B ) _OUT = _A;
end
else _OUT = _A;
end
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine