THOTAC25WL12.v
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// VERSION:1.00 DATE:2001/12/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module THOTAC25WL12 ( N01, H01, H02 );
input H01;
input H02;
output N01;
buf ( _H01, H01 );
buf ( _H02, H02 );
bufif1 ( _G001, _H01, _H02 );
bufif1 ( _G002, _G001, _H02 );
nmos ( _G002, N01_int, _G003 );
nmos ( N01, _G002, 1'b1 );
buf #1( _G004, N01 );
udp2up ( _G003, _H02, _G004 );
pullup ( N01_int );
specify
specparam DMY_SPC=1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
if ( !H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine