//VERSION: 2.2.0 DATE:02/01/09 RAM TYPE: 2port HD RAM
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module WBSRAMDHDWR32W32C2 (
	DO31,
	DO30,
	DO29,
	DO28,
	DO27,
	DO26,
	DO25,
	DO24,
	DO23,
	DO22,
	DO21,
	DO20,
	DO19,
	DO18,
	DO17,
	DO16,
	DO15,
	DO14,
	DO13,
	DO12,
	DO11,
	DO10,
	DO9,
	DO8,
	DO7,
	DO6,
	DO5,
	DO4,
	DO3,
	DO2,
	DO1,
	DO0,
	DI31,
	DI30,
	DI29,
	DI28,
	DI27,
	DI26,
	DI25,
	DI24,
	DI23,
	DI22,
	DI21,
	DI20,
	DI19,
	DI18,
	DI17,
	DI16,
	DI15,
	DI14,
	DI13,
	DI12,
	DI11,
	DI10,
	DI9,
	DI8,
	DI7,
	DI6,
	DI5,
	DI4,
	DI3,
	DI2,
	DI1,
	DI0,
	AA4,
	AA3,
	AA2,
	AA1,
	AA0,
	AB4,
	AB3,
	AB2,
	AB1,
	AB0,
	CSA,
	CSB,
	BEA,
	BEB,
	TBEA,
	TBEB,
	TEST,
	BUB
	);

    input DI0 ;
    input DI1 ;
    input DI2 ;
    input DI3 ;
    input DI4 ;
    input DI5 ;
    input DI6 ;
    input DI7 ;
    input DI8 ;
    input DI9 ;
    input DI10 ;
    input DI11 ;
    input DI12 ;
    input DI13 ;
    input DI14 ;
    input DI15 ;
    input DI16 ;
    input DI17 ;
    input DI18 ;
    input DI19 ;
    input DI20 ;
    input DI21 ;
    input DI22 ;
    input DI23 ;
    input DI24 ;
    input DI25 ;
    input DI26 ;
    input DI27 ;
    input DI28 ;
    input DI29 ;
    input DI30 ;
    input DI31 ;
    input AA0 ;
    input AA1 ;
    input AA2 ;
    input AA3 ;
    input AA4 ;
    input AB0 ;
    input AB1 ;
    input AB2 ;
    input AB3 ;
    input AB4 ;
    input CSA ;
    input CSB ;
    input BEA ;
    input BEB ;
    input TBEA ;
    input TBEB ;
    input TEST ;
    input BUB ;
    output DO0 ;
    output DO1 ;
    output DO2 ;
    output DO3 ;
    output DO4 ;
    output DO5 ;
    output DO6 ;
    output DO7 ;
    output DO8 ;
    output DO9 ;
    output DO10 ;
    output DO11 ;
    output DO12 ;
    output DO13 ;
    output DO14 ;
    output DO15 ;
    output DO16 ;
    output DO17 ;
    output DO18 ;
    output DO19 ;
    output DO20 ;
    output DO21 ;
    output DO22 ;
    output DO23 ;
    output DO24 ;
    output DO25 ;
    output DO26 ;
    output DO27 ;
    output DO28 ;
    output DO29 ;
    output DO30 ;
    output DO31 ;

    parameter BIT=32;
    parameter WORD=32;
    parameter ADD_BIT=5;
    parameter tOH= 566:857:1396;  // DO Hold

	wire[BIT-1:0] DI;
	wire[ADD_BIT-1:0] AA;
	wire[ADD_BIT-1:0] AB;

/* -------------------------- */
reg [BIT-1:0] DO;
reg [BIT-1:0] tmp_DO;

reg [ADD_BIT-1:0] addressa;
reg [ADD_BIT-1:0] addressb;
reg intcsa,pre_BEA,pre_TBEA;
reg intcsb,pre_BEB,pre_TBEB;

parameter all_X={BIT{1'bx}};

reg[BIT-1:0] memory[0:WORD-1];

// address "X" 
reg[ADD_BIT-1:0] x_add_num[0:ADD_BIT];
integer i,x_count;
integer same_add_err;

`ifdef  NEC_RTL_SIM
   parameter tACC = 1510 ;  // Dummy value 
   time      A_time,B_time; // add
   parameter tBEA_BEB_S=1336;    /* clock BEB - data BEA */
   parameter tBEB_BEA_S=1336;    /* clock BEA - data BEB */
   parameter tTBEA_TBEB_S=1336;  /* clock BEB - data BEA */
   parameter tTBEB_TBEA_S=1336;  /* clock BEA - data BEB */
`endif  // NEC_RTL_SIM

/* -------------------------- */

	// ------------------------------------- specify check flg
	wire normal_mode;
	wire test_mode;

`ifdef  NEC_RTL_SIM
`else
	reg notifier_wa;
	reg notifier_aa;
	reg notifier_wra;
	reg notifier_b;
	reg notifier_bwa;
	reg notifier_period_aa;
	reg notifier_period_b;
	reg notifier_same;
	reg notifier_samex;
`endif

`ifdef  NEC_RTL_SIM
    initial begin
      PrintRTLMsg;
    end
`endif

   initial begin
      same_add_err = 1'b0;
   end
	// ------------------------------------- dummy buffer
    buf ( _DI0, DI0 );
    buf ( _DI1, DI1 );
    buf ( _DI2, DI2 );
    buf ( _DI3, DI3 );
    buf ( _DI4, DI4 );
    buf ( _DI5, DI5 );
    buf ( _DI6, DI6 );
    buf ( _DI7, DI7 );
    buf ( _DI8, DI8 );
    buf ( _DI9, DI9 );
    buf ( _DI10, DI10 );
    buf ( _DI11, DI11 );
    buf ( _DI12, DI12 );
    buf ( _DI13, DI13 );
    buf ( _DI14, DI14 );
    buf ( _DI15, DI15 );
    buf ( _DI16, DI16 );
    buf ( _DI17, DI17 );
    buf ( _DI18, DI18 );
    buf ( _DI19, DI19 );
    buf ( _DI20, DI20 );
    buf ( _DI21, DI21 );
    buf ( _DI22, DI22 );
    buf ( _DI23, DI23 );
    buf ( _DI24, DI24 );
    buf ( _DI25, DI25 );
    buf ( _DI26, DI26 );
    buf ( _DI27, DI27 );
    buf ( _DI28, DI28 );
    buf ( _DI29, DI29 );
    buf ( _DI30, DI30 );
    buf ( _DI31, DI31 );
    buf ( _AA0, AA0 );
    buf ( _AA1, AA1 );
    buf ( _AA2, AA2 );
    buf ( _AA3, AA3 );
    buf ( _AA4, AA4 );
    buf ( _AB0, AB0 );
    buf ( _AB1, AB1 );
    buf ( _AB2, AB2 );
    buf ( _AB3, AB3 );
    buf ( _AB4, AB4 );
    buf ( _CSA, CSA );
    buf ( _CSB, CSB );
    buf ( _BEA, BEA );
    buf ( _BEB, BEB );
    buf ( _TBEA, TBEA );
    buf ( _TBEB, TBEB );
    buf ( _TEST, TEST );
    buf ( _BUB, BUB );

    buf ( DI[0], _DI0 );
    buf ( DI[1], _DI1 );
    buf ( DI[2], _DI2 );
    buf ( DI[3], _DI3 );
    buf ( DI[4], _DI4 );
    buf ( DI[5], _DI5 );
    buf ( DI[6], _DI6 );
    buf ( DI[7], _DI7 );
    buf ( DI[8], _DI8 );
    buf ( DI[9], _DI9 );
    buf ( DI[10], _DI10 );
    buf ( DI[11], _DI11 );
    buf ( DI[12], _DI12 );
    buf ( DI[13], _DI13 );
    buf ( DI[14], _DI14 );
    buf ( DI[15], _DI15 );
    buf ( DI[16], _DI16 );
    buf ( DI[17], _DI17 );
    buf ( DI[18], _DI18 );
    buf ( DI[19], _DI19 );
    buf ( DI[20], _DI20 );
    buf ( DI[21], _DI21 );
    buf ( DI[22], _DI22 );
    buf ( DI[23], _DI23 );
    buf ( DI[24], _DI24 );
    buf ( DI[25], _DI25 );
    buf ( DI[26], _DI26 );
    buf ( DI[27], _DI27 );
    buf ( DI[28], _DI28 );
    buf ( DI[29], _DI29 );
    buf ( DI[30], _DI30 );
    buf ( DI[31], _DI31 );

    buf ( AA[0], _AA0 );
    buf ( AA[1], _AA1 );
    buf ( AA[2], _AA2 );
    buf ( AA[3], _AA3 );
    buf ( AA[4], _AA4 );
    buf ( AB[0], _AB0 );
    buf ( AB[1], _AB1 );
    buf ( AB[2], _AB2 );
    buf ( AB[3], _AB3 );
    buf ( AB[4], _AB4 );

	wire [BIT-1:0] dmy_DO;
	assign dmy_DO=DO;

    nmos ( DO0, dmy_DO[0], 1'b1 );
    nmos ( DO1, dmy_DO[1], 1'b1 );
    nmos ( DO2, dmy_DO[2], 1'b1 );
    nmos ( DO3, dmy_DO[3], 1'b1 );
    nmos ( DO4, dmy_DO[4], 1'b1 );
    nmos ( DO5, dmy_DO[5], 1'b1 );
    nmos ( DO6, dmy_DO[6], 1'b1 );
    nmos ( DO7, dmy_DO[7], 1'b1 );
    nmos ( DO8, dmy_DO[8], 1'b1 );
    nmos ( DO9, dmy_DO[9], 1'b1 );
    nmos ( DO10, dmy_DO[10], 1'b1 );
    nmos ( DO11, dmy_DO[11], 1'b1 );
    nmos ( DO12, dmy_DO[12], 1'b1 );
    nmos ( DO13, dmy_DO[13], 1'b1 );
    nmos ( DO14, dmy_DO[14], 1'b1 );
    nmos ( DO15, dmy_DO[15], 1'b1 );
    nmos ( DO16, dmy_DO[16], 1'b1 );
    nmos ( DO17, dmy_DO[17], 1'b1 );
    nmos ( DO18, dmy_DO[18], 1'b1 );
    nmos ( DO19, dmy_DO[19], 1'b1 );
    nmos ( DO20, dmy_DO[20], 1'b1 );
    nmos ( DO21, dmy_DO[21], 1'b1 );
    nmos ( DO22, dmy_DO[22], 1'b1 );
    nmos ( DO23, dmy_DO[23], 1'b1 );
    nmos ( DO24, dmy_DO[24], 1'b1 );
    nmos ( DO25, dmy_DO[25], 1'b1 );
    nmos ( DO26, dmy_DO[26], 1'b1 );
    nmos ( DO27, dmy_DO[27], 1'b1 );
    nmos ( DO28, dmy_DO[28], 1'b1 );
    nmos ( DO29, dmy_DO[29], 1'b1 );
    nmos ( DO30, dmy_DO[30], 1'b1 );
    nmos ( DO31, dmy_DO[31], 1'b1 );

/* ----------------------- specify */
	assign normal_mode=((_BUB!==0) && (_TEST!==1));
	assign test_mode=((_BUB!==0) && (_TEST!==0));

`ifdef  NEC_RTL_SIM
`else
     wire _check_n1a;
     wire _check_t1a;
     wire _check_n1b;
     wire _check_t1b;
     wire _check_n2a;
     wire _check_t2a;
     wire _check_n2b;
     wire _check_t2b;
     wire _check_n3;
     wire _check_t3;
     wire _check_bubna;
     wire _check_bubnb;
     wire _check_bubta;
     wire _check_bubtb;
     wire _check_testa;
     wire _check_testb;

     wire _check_n4ab;
     wire _check_n4ba;
     wire _check_n4bax;
     wire _check_t4ab;
     wire _check_t4ba;
     wire _check_t4bax;
     wire _check_n4h;
     wire _check_t4h;

     wire _check_periodna;
     wire _check_periodta;
     wire _check_periodnb;
     wire _check_periodtb;
`endif

`ifdef  NEC_RTL_SIM
`else
     assign _check_n1a=((_CSA!==1'b1) && (normal_mode==1));
     assign _check_t1a=((_CSA!==1'b1) && (test_mode==1));
     assign _check_n1b=((_CSB!==1'b1) && (normal_mode==1));
     assign _check_t1b=((_CSB!==1'b1) && (test_mode==1));
     assign _check_n3=((normal_mode==1));
     assign _check_t3=((test_mode==1));
     assign _check_bubna=((_CSA!==1'b1) && (_TEST!==1'b1));
     assign _check_bubta=((_CSA!==1'b1) && (_TEST!==1'b0));
     assign _check_testa=((_CSA!==1'b1) && (_BUB!==1'b0));
     assign _check_bubnb=((_CSB!==1'b1) && (_TEST!==1'b1));
     assign _check_bubtb=((_CSB!==1'b1) && (_TEST!==1'b0));
     assign _check_testb=((_CSB!==1'b1) && (_BUB!==1'b0));

     assign _check_n4ab=((normal_mode==1) && (intcsa!==1'b1) && (addressa===AB) && (_CSB!==1'b1) );
     assign _check_n4ba=((normal_mode==1) && (intcsb===1'b0) && (addressb===AA) && (_CSA!==1'b1) );
     assign _check_n4bax=((normal_mode==1) && (intcsb===1'bx) && (_CSA!==1'b1) );
     assign _check_t4ab=((test_mode==1) && (intcsa!==1'b1) && (addressa===AB) && (_CSB!==1'b1) );
     assign _check_t4ba=((test_mode==1) && (intcsb===1'b0) && (addressb===AA) && (_CSA!==1'b1) );
     assign _check_t4bax=((test_mode==1) && (intcsb===1'bx) && (_CSA!==1'b1) );
     assign _check_n4h=((normal_mode==1) && (_CSA!==1'b1) && (AA===AB) && (_CSB!==1'b1) );
     assign _check_t4h=((test_mode==1) && (_CSA!==1'b1) && (AA===AB) && (_CSB!==1'b1) );

     buf #1 (pre_csa,intcsa);
     buf #1 (pre_csb,intcsb);

//     assign _check_periodna=((normal_mode==1) && (pre_csa!==1'b1));
//     assign _check_periodta=((test_mode==1))&& (pre_csa!==1'b1);
//     assign _check_periodnb=((normal_mode==1) && (pre_csb!==1'b1));
//     assign _check_periodtb=((test_mode==1) && (pre_csb!==1'b1));
     assign _check_periodna=((normal_mode==1));
     assign _check_periodta=((test_mode==1));
     assign _check_periodnb=((normal_mode==1));
     assign _check_periodtb=((test_mode==1));
`endif  // NEC_RTL_SIM

`ifdef  NEC_RTL_SIM
`else
    specify
        specparam DMY_SPC=1:1:1;
        specparam BEA_BEB_S=598:856:1336;    /* clock BEB - data BEA */
        specparam BEB_BEA_S=598:856:1336;    /* clock BEA - data BEB */
        specparam TBEA_TBEB_S=598:856:1336;  /* clock BEB - data BEA */
        specparam TBEB_TBEA_S=598:856:1336;  /* clock BEA - data BEB */


	$setup ( posedge DI0, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI1, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI2, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI3, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI4, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI5, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI6, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI7, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI8, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI9, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI10, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI11, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI12, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI13, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI14, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI15, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI16, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI17, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI18, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI19, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI20, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI21, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI22, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI23, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI24, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI25, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI26, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI27, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI28, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI29, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI30, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI31, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI0, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI1, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI2, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI3, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI4, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI5, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI6, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI7, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI8, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI9, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI10, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI11, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI12, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI13, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI14, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI15, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI16, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI17, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI18, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI19, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI20, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI21, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI22, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI23, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI24, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI25, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI26, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI27, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI28, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI29, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI30, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI31, posedge BEA &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI0 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI1 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI2 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI3 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI4 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI5 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI6 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI7 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI8 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI9 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI10 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI11 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI12 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI13 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI14 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI15 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI16 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI17 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI18 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI19 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI20 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI21 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI22 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI23 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI24 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI25 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI26 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI27 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI28 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI29 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI30 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, posedge DI31 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI0 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI1 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI2 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI3 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI4 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI5 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI6 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI7 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI8 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI9 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI10 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI11 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI12 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI13 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI14 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI15 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI16 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI17 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI18 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI19 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI20 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI21 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI22 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI23 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI24 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI25 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI26 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI27 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI28 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI29 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI30 &&& _check_n1a, DMY_SPC, notifier_wa );
	$hold ( posedge BEA, negedge DI31 &&& _check_n1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI0, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI1, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI2, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI3, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI4, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI5, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI6, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI7, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI8, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI9, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI10, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI11, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI12, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI13, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI14, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI15, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI16, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI17, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI18, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI19, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI20, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI21, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI22, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI23, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI24, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI25, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI26, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI27, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI28, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI29, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI30, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( posedge DI31, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI0, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI1, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI2, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI3, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI4, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI5, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI6, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI7, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI8, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI9, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI10, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI11, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI12, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI13, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI14, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI15, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI16, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI17, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI18, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI19, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI20, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI21, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI22, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI23, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI24, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI25, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI26, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI27, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI28, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI29, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI30, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$setup ( negedge DI31, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI0 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI1 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI2 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI3 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI4 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI5 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI6 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI7 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI8 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI9 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI10 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI11 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI12 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI13 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI14 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI15 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI16 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI17 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI18 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI19 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI20 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI21 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI22 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI23 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI24 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI25 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI26 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI27 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI28 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI29 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI30 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, posedge DI31 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI0 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI1 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI2 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI3 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI4 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI5 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI6 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI7 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI8 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI9 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI10 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI11 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI12 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI13 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI14 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI15 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI16 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI17 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI18 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI19 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI20 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI21 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI22 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI23 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI24 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI25 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI26 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI27 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI28 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI29 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI30 &&& _check_t1a, DMY_SPC, notifier_wa );
	$hold ( posedge TBEA, negedge DI31 &&& _check_t1a, DMY_SPC, notifier_wa );

	$setup ( posedge AA0, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA1, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA2, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA3, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA4, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA0, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA1, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA2, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA3, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA4, posedge BEA &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, posedge AA0 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, posedge AA1 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, posedge AA2 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, posedge AA3 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, posedge AA4 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, negedge AA0 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, negedge AA1 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, negedge AA2 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, negedge AA3 &&& _check_n1a, DMY_SPC, notifier_aa );
	$hold ( posedge BEA, negedge AA4 &&& _check_n1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA0, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA1, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA2, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA3, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( posedge AA4, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA0, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA1, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA2, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA3, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$setup ( negedge AA4, posedge TBEA &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, posedge AA0 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, posedge AA1 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, posedge AA2 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, posedge AA3 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, posedge AA4 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, negedge AA0 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, negedge AA1 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, negedge AA2 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, negedge AA3 &&& _check_t1a, DMY_SPC, notifier_aa );
	$hold ( posedge TBEA, negedge AA4 &&& _check_t1a, DMY_SPC, notifier_aa );

	$setup ( posedge AB0, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB1, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB2, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB3, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB4, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB0, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB1, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB2, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB3, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB4, posedge BEB &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, posedge AB0 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, posedge AB1 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, posedge AB2 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, posedge AB3 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, posedge AB4 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, negedge AB0 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, negedge AB1 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, negedge AB2 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, negedge AB3 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$hold ( posedge BEB, negedge AB4 &&& _check_n1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB0, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB1, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB2, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB3, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( posedge AB4, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB0, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB1, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB2, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB3, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$setup ( negedge AB4, posedge TBEB &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, posedge AB0 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, posedge AB1 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, posedge AB2 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, posedge AB3 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, posedge AB4 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, negedge AB0 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, negedge AB1 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, negedge AB2 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, negedge AB3 &&& _check_t1b, DMY_SPC, notifier_bwa );
	$hold ( posedge TBEB, negedge AB4 &&& _check_t1b, DMY_SPC, notifier_bwa );

        $setup ( posedge CSA, posedge BEA &&& _check_n3, DMY_SPC, notifier_aa );
        $setup ( negedge CSA, posedge BEA &&& _check_n3, DMY_SPC, notifier_aa );
        $hold ( posedge BEA, posedge CSA &&& _check_n3, DMY_SPC, notifier_aa );
        $hold ( posedge BEA, negedge CSA &&& _check_n3, DMY_SPC, notifier_aa );
        $setup ( posedge CSA, posedge TBEA &&& _check_t3, DMY_SPC, notifier_aa );
        $setup ( negedge CSA, posedge TBEA &&& _check_t3, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA, posedge CSA &&& _check_t3, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA, negedge CSA &&& _check_t3, DMY_SPC, notifier_aa );

        $setup ( posedge CSB, posedge BEB &&& _check_n3, DMY_SPC, notifier_bwa );
        $setup ( negedge CSB, posedge BEB &&& _check_n3, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB, posedge CSB &&& _check_n3, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB, negedge CSB &&& _check_n3, DMY_SPC, notifier_bwa );
        $setup ( posedge CSB, posedge TBEB &&& _check_t3, DMY_SPC, notifier_bwa );
        $setup ( negedge CSB, posedge TBEB &&& _check_t3, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB, posedge CSB &&& _check_t3, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB, negedge CSB &&& _check_t3, DMY_SPC, notifier_bwa );

        $width ( posedge BEA &&& _check_n1a, DMY_SPC, 0, notifier_wra );
        $width ( negedge BEA &&& _check_n1a, DMY_SPC, 0, notifier_aa );
        $width ( posedge TBEA &&& _check_t1a, DMY_SPC, 0, notifier_wra );
        $width ( negedge TBEA &&& _check_t1a, DMY_SPC, 0, notifier_aa );

        $width ( posedge BEB &&& _check_n1b, DMY_SPC, 0, notifier_b );
        $width ( negedge BEB &&& _check_n1b, DMY_SPC, 0, notifier_bwa );
        $width ( posedge TBEB &&& _check_t1b, DMY_SPC, 0, notifier_b );
        $width ( negedge TBEB &&& _check_t1b, DMY_SPC, 0, notifier_bwa );

        $setup ( posedge BUB, posedge BEA &&& _check_bubna, DMY_SPC, notifier_aa );
        $setup ( negedge BUB, posedge BEA &&& _check_bubna, DMY_SPC, notifier_aa );
        $hold ( posedge BEA &&& _check_bubna, posedge BUB, DMY_SPC, notifier_aa );
        $hold ( posedge BEA &&& _check_bubna, negedge BUB, DMY_SPC, notifier_aa );
        $setup ( posedge BUB, negedge BEA &&& _check_bubna, DMY_SPC, notifier_aa );
        $setup ( negedge BUB, negedge BEA &&& _check_bubna, DMY_SPC, notifier_aa );
        $hold ( negedge BEA &&& _check_bubna, posedge BUB, DMY_SPC, notifier_aa );
        $hold ( negedge BEA &&& _check_bubna, negedge BUB, DMY_SPC, notifier_aa );

        $setup ( posedge TEST, posedge BEA &&& _check_testa, DMY_SPC, notifier_aa );
        $setup ( negedge TEST, posedge BEA &&& _check_testa, DMY_SPC, notifier_aa );
        $hold ( posedge BEA &&& _check_testa, posedge TEST, DMY_SPC, notifier_aa );
        $hold ( posedge BEA &&& _check_testa, negedge TEST, DMY_SPC, notifier_aa );
        $setup ( posedge TEST, negedge BEA &&& _check_testa, DMY_SPC, notifier_aa );
        $setup ( negedge TEST, negedge BEA &&& _check_testa, DMY_SPC, notifier_aa );
        $hold ( negedge BEA &&& _check_testa, posedge TEST, DMY_SPC, notifier_aa );
        $hold ( negedge BEA &&& _check_testa, negedge TEST, DMY_SPC, notifier_aa );

        $setup ( posedge BUB, posedge TBEA &&& _check_bubta, DMY_SPC, notifier_aa );
        $setup ( negedge BUB, posedge TBEA &&& _check_bubta, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA &&& _check_bubta, posedge BUB, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA &&& _check_bubta, negedge BUB, DMY_SPC, notifier_aa );
        $setup ( posedge BUB, negedge TBEA &&& _check_bubta, DMY_SPC, notifier_aa );
        $setup ( negedge BUB, negedge TBEA &&& _check_bubta, DMY_SPC, notifier_aa );
        $hold ( negedge TBEA &&& _check_bubta, posedge BUB, DMY_SPC, notifier_aa );
        $hold ( negedge TBEA &&& _check_bubta, negedge BUB, DMY_SPC, notifier_aa );

        $setup ( posedge TEST, posedge TBEA &&& _check_testa, DMY_SPC, notifier_aa );
        $setup ( negedge TEST, posedge TBEA &&& _check_testa, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA &&& _check_testa, posedge TEST, DMY_SPC, notifier_aa );
        $hold ( posedge TBEA &&& _check_testa, negedge TEST, DMY_SPC, notifier_aa );
        $setup ( posedge TEST, negedge TBEA &&& _check_testa, DMY_SPC, notifier_aa );
        $setup ( negedge TEST, negedge TBEA &&& _check_testa, DMY_SPC, notifier_aa );
        $hold ( negedge TBEA &&& _check_testa, posedge TEST, DMY_SPC, notifier_aa );
        $hold ( negedge TBEA &&& _check_testa, negedge TEST, DMY_SPC, notifier_aa );

        $setup ( posedge BUB, posedge BEB &&& _check_bubnb, DMY_SPC, notifier_bwa );
        $setup ( negedge BUB, posedge BEB &&& _check_bubnb, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB &&& _check_bubnb, posedge BUB, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB &&& _check_bubnb, negedge BUB, DMY_SPC, notifier_bwa );
        $setup ( posedge BUB, negedge BEB &&& _check_bubnb, DMY_SPC, notifier_bwa );
        $setup ( negedge BUB, negedge BEB &&& _check_bubnb, DMY_SPC, notifier_bwa );
        $hold ( negedge BEB &&& _check_bubnb, posedge BUB, DMY_SPC, notifier_bwa );
        $hold ( negedge BEB &&& _check_bubnb, negedge BUB, DMY_SPC, notifier_bwa );

        $setup ( posedge TEST, posedge BEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $setup ( negedge TEST, posedge BEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB &&& _check_testb, posedge TEST, DMY_SPC, notifier_bwa );
        $hold ( posedge BEB &&& _check_testb, negedge TEST, DMY_SPC, notifier_bwa );
        $setup ( posedge TEST, negedge BEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $setup ( negedge TEST, negedge BEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $hold ( negedge BEB &&& _check_testb, posedge TEST, DMY_SPC, notifier_bwa );
        $hold ( negedge BEB &&& _check_testb, negedge TEST, DMY_SPC, notifier_bwa );

        $setup ( posedge BUB, posedge TBEB &&& _check_bubtb, DMY_SPC, notifier_bwa );
        $setup ( negedge BUB, posedge TBEB &&& _check_bubtb, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB &&& _check_bubtb, posedge BUB, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB &&& _check_bubtb, negedge BUB, DMY_SPC, notifier_bwa );
        $setup ( posedge BUB, negedge TBEB &&& _check_bubtb, DMY_SPC, notifier_bwa );
        $setup ( negedge BUB, negedge TBEB &&& _check_bubtb, DMY_SPC, notifier_bwa );
        $hold ( negedge TBEB &&& _check_bubtb, posedge BUB, DMY_SPC, notifier_bwa );
        $hold ( negedge TBEB &&& _check_bubtb, negedge BUB, DMY_SPC, notifier_bwa );

        $setup ( posedge TEST, posedge TBEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $setup ( negedge TEST, posedge TBEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB &&& _check_testb, posedge TEST, DMY_SPC, notifier_bwa );
        $hold ( posedge TBEB &&& _check_testb, negedge TEST, DMY_SPC, notifier_bwa );
        $setup ( posedge TEST, negedge TBEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $setup ( negedge TEST, negedge TBEB &&& _check_testb, DMY_SPC, notifier_bwa );
        $hold ( negedge TBEB &&& _check_testb, posedge TEST, DMY_SPC, notifier_bwa );
        $hold ( negedge TBEB &&& _check_testb, negedge TEST, DMY_SPC, notifier_bwa );

      // -------- BEA(R), period */
        $period ( posedge BEA &&& _check_periodna, DMY_SPC, notifier_period_aa );
        $period ( posedge TBEA &&& _check_periodta, DMY_SPC, notifier_period_aa );
        $period ( posedge BEB &&& _check_periodnb, DMY_SPC, notifier_period_b );
        $period ( posedge TBEB &&& _check_periodtb, DMY_SPC, notifier_period_b );

      // -------- BEA(R), BEB(R) setup/hold
      $setup ( posedge BEA, posedge BEB &&& _check_n4ab, BEA_BEB_S, notifier_same );
      $setup ( posedge BEB, posedge BEA &&& _check_n4ba, BEB_BEA_S, notifier_same );
      $setup ( posedge BEB, posedge BEA &&& _check_n4bax, BEB_BEA_S, notifier_samex );
      $hold ( posedge BEB &&& _check_n4h, posedge BEA, 1, notifier_same );
      // -------- TBEA(R), TBEB(R) setup/hold
      $setup ( posedge TBEA, posedge TBEB &&& _check_t4ab, TBEA_TBEB_S, notifier_same );
      $setup ( posedge TBEB, posedge TBEA &&& _check_t4ba, TBEB_TBEA_S, notifier_same );
      $setup ( posedge TBEB, posedge TBEA &&& _check_t4bax, TBEB_TBEA_S, notifier_samex );
      $hold ( posedge TBEB &&& _check_t4h, posedge TBEA, 1, notifier_same );

// <-- new spec

	( BEB => DO0 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO1 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO2 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO3 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO4 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO5 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO6 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO7 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO8 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO9 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO10 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO11 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO12 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO13 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO14 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO15 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO16 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO17 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO18 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO19 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO20 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO21 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO22 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO23 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO24 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO25 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO26 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO27 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO28 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO29 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO30 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( BEB => DO31 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC, DMY_SPC );
	( TBEB => DO0 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO1 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO2 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO3 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO4 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO5 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO6 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO7 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO8 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO9 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO10 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO11 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO12 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO13 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO14 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO15 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO16 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO17 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO18 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO19 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO20 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO21 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO22 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO23 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO24 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO25 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO26 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO27 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO28 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO29 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO30 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );
	( TBEB => DO31 ) = ( DMY_SPC, DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC , DMY_SPC );

        // ------------ ( BUB,TEST,BUNRI => DO,TDO )= ?->"x" or "x"->? or Z
	(BUB=> DO0)=1;
	(BUB=> DO1)=1;
	(BUB=> DO2)=1;
	(BUB=> DO3)=1;
	(BUB=> DO4)=1;
	(BUB=> DO5)=1;
	(BUB=> DO6)=1;
	(BUB=> DO7)=1;
	(BUB=> DO8)=1;
	(BUB=> DO9)=1;
	(BUB=> DO10)=1;
	(BUB=> DO11)=1;
	(BUB=> DO12)=1;
	(BUB=> DO13)=1;
	(BUB=> DO14)=1;
	(BUB=> DO15)=1;
	(BUB=> DO16)=1;
	(BUB=> DO17)=1;
	(BUB=> DO18)=1;
	(BUB=> DO19)=1;
	(BUB=> DO20)=1;
	(BUB=> DO21)=1;
	(BUB=> DO22)=1;
	(BUB=> DO23)=1;
	(BUB=> DO24)=1;
	(BUB=> DO25)=1;
	(BUB=> DO26)=1;
	(BUB=> DO27)=1;
	(BUB=> DO28)=1;
	(BUB=> DO29)=1;
	(BUB=> DO30)=1;
	(BUB=> DO31)=1;
	(TEST=> DO0)=1;
	(TEST=> DO1)=1;
	(TEST=> DO2)=1;
	(TEST=> DO3)=1;
	(TEST=> DO4)=1;
	(TEST=> DO5)=1;
	(TEST=> DO6)=1;
	(TEST=> DO7)=1;
	(TEST=> DO8)=1;
	(TEST=> DO9)=1;
	(TEST=> DO10)=1;
	(TEST=> DO11)=1;
	(TEST=> DO12)=1;
	(TEST=> DO13)=1;
	(TEST=> DO14)=1;
	(TEST=> DO15)=1;
	(TEST=> DO16)=1;
	(TEST=> DO17)=1;
	(TEST=> DO18)=1;
	(TEST=> DO19)=1;
	(TEST=> DO20)=1;
	(TEST=> DO21)=1;
	(TEST=> DO22)=1;
	(TEST=> DO23)=1;
	(TEST=> DO24)=1;
	(TEST=> DO25)=1;
	(TEST=> DO26)=1;
	(TEST=> DO27)=1;
	(TEST=> DO28)=1;
	(TEST=> DO29)=1;
	(TEST=> DO30)=1;
	(TEST=> DO31)=1;
    endspecify
`endif  // NEC_RTL_SIM

/* ************************** */

// ----------------------------------------- timing error
`ifdef  NEC_RTL_SIM
`else
always @ ( notifier_wa ) begin
    addressa=AA;
    WriteAddressAXCount;
    if (x_count !== 0) WriteAddAX;
    else memory[addressa]=all_X;
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
end

always @ ( notifier_aa ) begin
    addressa=AA;
    MemWriteX;
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
    /* B port Unkown */
    disable FUNCTB_NORMAL;
    disable FUNCTB_TEST;
    tmp_DO=all_X;
    DO=all_X;
end

always @ ( notifier_period_aa ) begin
    if ( pre_csa !== 1 ) begin
    addressa=AA;
    MemWriteX;
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
    disable FUNCTB_NORMAL;
    disable FUNCTB_TEST;
    tmp_DO=all_X;
    DO=all_X;
    end
end

always @ ( notifier_b ) begin
    addressb=AB;
    /* A port Unkown */
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
    disable FUNCTB_NORMAL;
    disable FUNCTB_TEST;
    tmp_DO=all_X;
    DO=all_X;
end

always @ ( notifier_bwa ) begin
    addressb=AB;
    MemWriteX;
    /* A port Unkown */
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
    disable FUNCTB_NORMAL;
    disable FUNCTB_TEST;
    tmp_DO=all_X;
    DO=all_X;
end
always @ ( notifier_period_b ) begin
    if ( pre_csb !== 1 ) begin
    MemWriteX;
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
    disable FUNCTB_NORMAL;
    disable FUNCTB_TEST;
    tmp_DO=all_X;
    DO=all_X;
    end
end

always @ ( notifier_wra ) begin
    addressa=AA;
        WriteAddressAXCount;
        if (x_count !== 0) WriteAddAX;
        else memory[addressa]=all_X;
    disable FUNCTA_NORMAL;
    disable FUNCTA_TEST;
end

always @ ( notifier_same ) begin
        disable FUNCTB_NORMAL;
        disable FUNCTB_TEST;
        DO=all_X;
    	tmp_DO=all_X;
end

always @ ( notifier_samex ) begin
        addressa=AA;
        WriteAddressAXCount;
        if (x_count !== 0) WriteAddAX;
        else memory[addressa]=all_X;
        disable FUNCTB_NORMAL;
        disable FUNCTB_TEST;
        DO=all_X;
        tmp_DO=all_X;
end
`endif  // NEC_RTL_SIM

// ----------------------------------------- ram function

always @ ( _TEST ) begin
	   pre_BEA = _BEA ;
	   pre_TBEA = _TBEA ;
	   pre_BEB = _BEB ;
	   pre_TBEB = _TBEB ;
	   if ( _BUB!==1'b0 && (_BEA!==1'b0 || _TBEA!==1'b0)
					&& intcsa!==1'b1) begin
    		MemWriteX;
	   end
	   else if ( _TEST===1'bx) begin
    		if ( _CSA!==1'b1 && (_BEA!==1'b0 || _TBEA!==1'b0) ) begin
	  	   MemWriteX;
    		end
	   end
	   if ( _BUB!==1'b0 && (_BEB!==1'b0 || _TBEB!==1'b0)
					&& intcsb!==1'b1) begin
                MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST===1'bx) begin
    		DO=all_X;
    		tmp_DO=all_X;
    		if ( _CSB!==1'b1 && (_BEB!==1'b0 || _TBEB!==1'b0) ) begin
                   MemWriteX;
    	  	   tmp_DO=all_X;
          	   DO=all_X;
    		end
	   end
end

always @ ( _BUB ) begin
	   pre_BEA = _BEA ;
	   pre_TBEA = _TBEA ;
	   pre_BEB = _BEB ;
	   pre_TBEB = _TBEB ;
	   if ( _BUB===1'bx) begin
    		MemWriteX;
	   end
	   else if ( _TEST!==1'b1 && _BEA!==1'b0 && intcsa!==1'b1) begin
    		MemWriteX;
	   end
	   else if ( _TEST!==1'b0 && _TBEA!==1'b0 && intcsa!==1'b1) begin
    		MemWriteX;
	   end
	   else if ( _BUB===1'b0) begin
	   end
	   if ( _BUB===1'bx) begin
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST!==1'b1 && _BEB!==1'b0 && intcsb!==1'b1) begin
                MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST!==1'b0 && _TBEB!==1'b0 && intcsb!==1'b1) begin
                MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _BUB===1'b0) begin
		DO=all_X;
	   end
end

// ---------------------------------------- _CSA change on BEA/TBEA=X
always @ ( _CSA ) begin
  if ((_BEA===1'bx) && (_CSA!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b1)) begin
    MemWriteX;
  end
  if ((_TBEA===1'bx) && (_CSA!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b0)) begin
    MemWriteX;
  end
end
// ---------------------------------------- _CSB change on BEB/TBEB=X
always @ ( _CSB ) begin
  if ((_BEB===1'bx) && (_CSB!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b1)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
  if ((_TBEB===1'bx) && (_CSB!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b0)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
end

// ---------------------------------- function
always @ ( _BEA ) begin : FUNCTA_NORMAL
  if ( (_BUB===1'b1) && (_TEST===1'b0)) begin // --- normal mode
     casez ( {pre_BEA,_BEA} )
	2'b01 : begin // -------------- 0->1 posedge
           addressa=AA;
           intcsa=_CSA;

	`ifdef  NEC_RTL_SIM
	   `ifdef  NEC_NO_SAME_ADD_CHECK
	   `else
	      same_add_err = 1'b0;
	      RC_checkA;
	   `endif
	`endif

	   ////
	   if ( _CSA===1'b0) begin
	      if (addressa > (WORD-1)) PrintWMsg_1;
	      WriteAddressAXCount;
	      ///
	      if (x_count !== 0) begin
		WriteAddAX;
	      end
	      ///
              //
              else if ( _BEB===1'bx && _CSB!==1'b1) begin
                WriteAddAX;
              end
              //
	      else begin
		 memory[addressa]=DI;
		 `ifdef  NEC_RTL_SIM
		    `ifdef  NEC_NO_SAME_ADD_CHECK
		    `else
		       if (same_add_err !== 1'b0) begin
			  DO=all_X;
			  tmp_DO=all_X;
		       end
		    `endif
	         `endif
	      end
	      ///
	   end
	   ////
	   else if ( _CSA===1'bx) begin
	         MemWriteX;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           intcsa=1'bx;
	   if ( _CSA!==1'b1) begin
	         MemWriteX;
	   end
	end
     endcase
	   pre_BEA = _BEA ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSA!==1'b1 && _BEA!==1'b1) begin
	  pre_BEA = _BEA ;
          intcsa=1'bx;
	  MemWriteX;
    end
  end

end

// ---------------------------------- normal b function
always @ ( _BEB ) begin : FUNCTB_NORMAL
  if ( (_BUB===1'b1) && (_TEST===1'b0)) begin // --- normal mode
     casez ( {pre_BEB,_BEB} )
	2'b01 : begin // -------------- 0->1 posedge
           addressb=AB;
           intcsb=_CSB;

	   `ifdef  NEC_RTL_SIM
	      `ifdef  NEC_NO_SAME_ADD_CHECK
	       `else
		  same_add_err = 1'b0;
		  RC_checkB;
	       `endif
	   `endif

	   ////
	   if ( _CSB===1'b0) begin
	      if (addressb > (WORD-1)) PrintWMsg_1;
              WriteAddressBXCount;
	      ///
	         //
	         if ( _BEA===1'bx && _CSA!==1'b1) begin
    		    tmp_DO=all_X;
                    DO=tmp_DO;
	         end
	         //
	         else begin
                   ///
                   if (x_count !== 0) begin
                      WriteAddBX;
                   end
                   ///
            	   tmp_DO=memory[addressb];
// add
`ifdef  NEC_RTL_SIM
		    `ifdef  NEC_NO_SAME_ADD_CHECK
		       #(tACC) DO = tmp_DO;
		    `else
		       if (same_add_err !== 1'b0) begin
			  DO=all_X;
			  tmp_DO=all_X;
		       end
		       else begin
			  #(tACC) DO = tmp_DO;
		       end
		    `endif
`else
                   if ( DO === tmp_DO ) begin
                       DO=tmp_DO;
                   end
                   else begin
                     if (DO===all_X) begin
                       DO=tmp_DO;
                     end
                     else begin
			DO={BIT{1'bx}};
			#1;
			if (DO===all_X) begin
			   DO=tmp_DO;
			end
                     end
                   end
`endif  // NEC_RTL_SIM
                 end
// add
	         //
	      ///
	   end
	   ////
	   else if ( _CSB===1'bx) begin
                 MemWriteX;
    		 tmp_DO=all_X;
                 DO=tmp_DO;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           intcsb=1'bx;
	   if ( _CSB!==1'b1) begin
                 MemWriteX;
    		 tmp_DO=all_X;
                 DO=tmp_DO;
	   end
	end
     endcase
	   pre_BEB = _BEB ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSB!==1'b1 && _BEB!==1'b1) begin
          MemWriteX;
	  pre_BEB = _BEB ;
          intcsb=1'bx;
    	  tmp_DO=all_X;
          DO=all_X;
    end
  end

end

// ---------------------------------- Test mode function (mode==4 only)
always @ ( _TBEA ) begin : FUNCTA_TEST
  if ( (_BUB===1'b1) && (_TEST===1'b1)) begin // --- normal mode
     casez ( {pre_TBEA,_TBEA} )
	2'b01 : begin // -------------- 0->1 posedge
           addressa=AA;
           intcsa=_CSA;

	`ifdef  NEC_RTL_SIM
	   `ifdef  NEC_NO_SAME_ADD_CHECK
	   `else
	      same_add_err=1'b0;
	      RC_checkTA;
	   `endif
	`endif

	   ////
	   if ( _CSA===1'b0) begin
	      if (addressa > (WORD-1)) PrintWMsg_1;
	      WriteAddressAXCount;
	      ///
	      if (x_count !== 0) begin
		WriteAddAX;
	      end
	      ///
              //
              else if ( _TBEB===1'bx && _CSB!==1'b1) begin
                WriteAddAX;
              end
              //
	      else begin
		 memory[addressa]=DI;
		 `ifdef  NEC_RTL_SIM
		    `ifdef  NEC_NO_SAME_ADD_CHECK
		    `else
		       if (same_add_err !== 1'b0) begin
			  DO=all_X;
			  tmp_DO=all_X;
		       end
		    `endif
	         `endif
	      end
	      ///
	   end
	   ////
	   else if ( _CSA===1'bx) begin
	         MemWriteX;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           intcsa=1'bx;
	   if ( _CSA!==1'b1) begin
	         MemWriteX;
	   end
	end
     endcase
	   pre_TBEA = _TBEA ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSA!==1'b1 && _TBEA!==1'b1) begin
	  pre_TBEA = _TBEA ;
          intcsa=1'bx;
	  MemWriteX;
    end
  end

end

// ---------------------------------- Test mode function (mode==4 only)
always @ ( _TBEB ) begin : FUNCTB_TEST
  if ( (_BUB===1'b1) && (_TEST===1'b1)) begin // --- normal mode
     casez ( {pre_TBEB,_TBEB} )
	2'b01 : begin // -------------- 0->1 posedge
           addressb=AB;
           intcsb=_CSB;

	`ifdef  NEC_RTL_SIM
   	   `ifdef  NEC_NO_SAME_ADD_CHECK
   	   `else
	      same_add_err=1'b0;
	      RC_checkTB;
    	   `endif
	`endif

	   ////
	   if ( _CSB===1'b0) begin
	      if (addressb > (WORD-1)) PrintWMsg_1;
              WriteAddressBXCount;
		 //
	         if ( _TBEA===1'bx && _CSA!==1'b1) begin
    		    tmp_DO=all_X;
                    DO=tmp_DO;
	         end
	         //
	         else  begin
                   ///
                   if (x_count !== 0) begin
                      WriteAddBX;
                   end
                   ///
            	   tmp_DO=memory[addressb];
`ifdef  NEC_RTL_SIM
		    `ifdef  NEC_NO_SAME_ADD_CHECK
		       #(tACC) DO = tmp_DO;
		    `else
		       if (same_add_err !== 1'b0) begin
			  DO=all_X;
			  tmp_DO=all_X;
		       end
		       else begin
			  #(tACC) DO = tmp_DO;
		       end
		    `endif
`else
                   if ( DO === tmp_DO ) begin
                       DO=tmp_DO;
                   end
                   else begin
                     if (DO===all_X) begin
                       DO=tmp_DO;
                     end
                     else begin
			DO={BIT{1'bx}};
			#1;
			if (DO===all_X) begin
			   DO=tmp_DO;
			end
		     end
		   end
`endif  // NEC_RTL_SIM
                 end
// add
	         //
	   end
	   ////
	   else if ( _CSB===1'bx) begin
                 MemWriteX;
    		 tmp_DO=all_X;
                 DO=tmp_DO;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           intcsb=1'bx;
	   if ( _CSB!==1'b1) begin
                 MemWriteX;
    		 tmp_DO=all_X;
                 DO=tmp_DO;
	   end
	end
     endcase
	   pre_TBEB = _TBEB ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSB!==1'b1 && _TBEB!==1'b1) begin
          MemWriteX;
	  pre_TBEB = _TBEB ;
          intcsb=1'bx;
    	  tmp_DO=all_X;
          DO=all_X;
    end
  end

end
// ---------------------------------- Test mode function (mode==4 only)

/* ----------------------------------- "x" conunt task */
task WriteAddressAXCount;
begin
    x_count=0;                              // write address "x" count
    for (i=0;i<ADD_BIT;i=i+1) begin
        if (addressa[i]===1'bx) begin
            x_add_num[x_count]=i;
            x_count=x_count+1;
        end
    end
end
endtask
task WriteAddressBXCount;
begin
    x_count=0;                              // write address "x" count
    for (i=0;i<ADD_BIT;i=i+1) begin
        if (addressb[i]===1'bx) begin
            x_add_num[x_count]=i;
            x_count=x_count+1;
        end
    end
end
endtask

/* ----------------------------------- find address & write task */
task WriteAddAX;

reg[ADD_BIT-1:0] new_address;
reg[ADD_BIT-1:0] b_count,num_count;
integer j,k,m;

begin
    new_address=addressa;
    b_count=(2<<(x_count-1))-1;
    num_count={ADD_BIT{1'b0}};
    for (j=0;j<=b_count;j=j+1) begin
        for (k=0;k<x_count;k=k+1) begin
            new_address[x_add_num[k]] = num_count[k];
            memory[new_address]=all_X;
        end
        num_count=num_count+1;
    end
end
endtask
task WriteAddBX;

reg[ADD_BIT-1:0] new_address;
reg[ADD_BIT-1:0] b_count,num_count;
integer j,k,m;

begin
    new_address=addressb;
    b_count=(2<<(x_count-1))-1;
    num_count={ADD_BIT{1'b0}};
    for (j=0;j<=b_count;j=j+1) begin
        for (k=0;k<x_count;k=k+1) begin
            new_address[x_add_num[k]] = num_count[k];
            memory[new_address]=all_X;
        end
        num_count=num_count+1;
    end
end
endtask

/* ------------ write x in all address */
task MemWriteX;
integer i;
begin
  for(i=0;i<WORD;i=i+1) memory[i]=all_X;
end
endtask

/* ------------ access invalid address warning message */
task PrintWMsg_1;
begin
	$display( $time,,"%m #### You are accessing the invalid address.\n");
end
endtask

`ifdef  NEC_RTL_SIM
task  PrintRTLMsg;
begin
	$display("===============================================");
	$display("Pure Behavior Function Mode : WBSRAMDHDWR32W32C2");
	$display("Instance       : %m");
	$display("Abstract Delay :");
	$display("   tACC        : %d",tACC);
 	$display("===============================================");
end
endtask
`endif

/* ************************** */

`ifdef  NEC_RTL_SIM
task RC_checkA;
begin
   A_time=$time;
   if ( (A_time===B_time) && (_CSA!==1) && (_CSB!==1) && (A_time===$time) && ((AA!=AB) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AA);
      same_add_err = 1'b1;
   end
   else if ( (A_time - B_time < tBEB_BEA_S ) && (_CSA!==1) && (intcsb!==1) && (A_time===$time) && ((AA!=addressb) ? 0 : 0) ) begin
      $display("%t: %m A and B ports are accessed same address %b", $time, AA);
      same_add_err = 1'b1;
   end
end
endtask

task RC_checkB;
begin
   B_time=$time;
   if ( (A_time===B_time) && (_CSB!==1) && (_CSA!==1) && (B_time===$time) && ((AA!=AB) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AB);
      same_add_err = 1'b1;
   end
   else if ( (B_time - A_time < tBEA_BEB_S ) && (intcsa!==1) && (_CSB!==1) && (B_time===$time) && ((AB!=addressa) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AB);
      same_add_err = 1'b1;
   end
end
endtask

task RC_checkTA;
begin
   A_time=$time;
   if ( (A_time===B_time) && (_CSA!==1) && (_CSB!==1) && (A_time===$time) && ((AA!=AB) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AA);
      same_add_err = 1'b1;
   end
   else if ( (A_time - B_time < tTBEB_TBEA_S ) && (_CSA!==1) && (intcsb!==1) && (A_time===$time) && ((AA!=addressb) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AA);
      same_add_err = 1'b1;
   end
end
endtask

task RC_checkTB;
begin
   B_time=$time;
   if ( (A_time===B_time) && (_CSB!==1) && (_CSA!==1) && (B_time===$time) && ((AA!=AB) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AB);
      same_add_err = 1'b1;
   end
   else if ( (B_time - A_time < tTBEA_TBEB_S ) && (intcsa!==1) && (_CSB!==1) && (B_time===$time) && ((AB!=addressa) ? 0 : 0) ) begin
      $display("%t: %m A and B ports  are accessed same address %b", $time, AB);
      same_add_err = 1'b1;
   end
end
endtask
`endif

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine