TBBSSTA2X4.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBBSSTA2X4 ( BSCON, H01, H02, H03, H04, H05 );
input H01;
input H02;
input H03;
input H04;
input H05;
output BSCON;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
not ( _G001, _H03 );
and ( _G002, _H01, _H02 );
and ( _G003, _H01, _G001 );
and ( _G004, _H02, _H03 );
or ( _G005, _G002, _G003, _G004 );
not ( _G006, _H05 );
and ( _G007, _G005, _H04 );
and ( _G008, _G005, _G006 );
and ( _G009, _H04, _H05 );
or ( BSCON, _G007, _G008, _G009 );
specify
specparam DMY_SPC=1;
( H01 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H02 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H04 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( H05 )
( H05 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( !H05 )
( H05 *> BSCON ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine