TDSECLPCX2.v
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// VERSION:1.00 DATE:00/09/20 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSECLPCX2 ( N01, N02, H01, H02, H03, H04, H05, H06 );
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
output N01;
output N02;
reg notif_lssd,notifier;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
not ( _H02N, _H02 );
not ( _H03N, _H03 );
and ( _G001, _H02, _H05 );
LSSD lssd ( _G003, _G002, _H01, _H03N, _H02N, _H04, notif_lssd, 1'b1 );
DLSFQ_LSSD2 q_out ( _G004, 1'b1, 1'b1, _G003, _G002, notif_lssd, 1'b1 );
DLSFQ ( _G005, _G004, _G001, 1'b1, 1'b1, notifier );
udp_MUX ( N01, _H06, _H01, _G005 );
DLSFQB ( _G006, _G004, _G001, 1'b1, 1'b1, notifier );
bufif1 ( _G007, _G006, _H06 );
buf ( N02, _G007 );
// Timing Check Flag
wire docheck1 = ( _H02 !== 1'b0 );
wire docheck2 = ( _H04 !== 1'b1 );
wire docheck3 = ( _H05 !== 1'b0 );
specify
specparam DMY_SPC=1;
$setup( posedge H01, posedge H02 &&& docheck2, DMY_SPC, notif_lssd );
$setup( negedge H01, posedge H02 &&& docheck2, DMY_SPC, notif_lssd );
$hold( posedge H02, posedge H01 &&& docheck2, DMY_SPC, notif_lssd );
$hold( posedge H02, negedge H01 &&& docheck2, DMY_SPC, notif_lssd );
$setup( posedge H03, negedge H04 &&& docheck1, DMY_SPC, notif_lssd );
$setup( negedge H03, negedge H04 &&& docheck1, DMY_SPC, notif_lssd );
$hold( negedge H04, posedge H03 &&& docheck1, DMY_SPC, notif_lssd );
$hold( negedge H04, negedge H03 &&& docheck1, DMY_SPC, notif_lssd );
$width ( negedge H02 &&& docheck2, DMY_SPC, 0, notif_lssd );
$width ( posedge H04 &&& docheck1, DMY_SPC, 0, notif_lssd );
$width ( posedge H02 &&& docheck3, DMY_SPC, 0, notifier );
$width ( posedge H05 &&& docheck1, DMY_SPC, 0, notifier );
( H01 => N01 ) = ( DMY_SPC, DMY_SPC );
( H02 => N01 ) = ( DMY_SPC, DMY_SPC );
( H02 => N02 ) = ( DMY_SPC, DMY_SPC );
( H05 => N01 ) = ( DMY_SPC, DMY_SPC );
( H05 => N02 ) = ( DMY_SPC, DMY_SPC );
if ( H06 )
( H06 => N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H06 )
( H06 => N01 ) = ( DMY_SPC, DMY_SPC );
( H03, H04 *> N01, N02 ) = ( 1:1:1, 1:1:1 );
( H06 => N02 ) = ( 1:1:1, 1:1:1 );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine