TBLAHAX2.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBLAHAX2 ( N01, N02, H01, H02 );
input H01;
input H02;
output N01;
output N02;
reg notifier;
reg docheck;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( N01, _G003 );
buf ( N02, _G003N );
DLSFQ ( _G003, _H01, _H02, 1'b1, 1'b1, notifier );
DLSFQB ( _G003N, _H01, _H02, 1'b1, 1'b1, notifier );
buf #1 ( _G099, _G003 );
`ifdef INCA
buf #1 ( _docheck, docheck );
`else
`ifdef VCS
buf #1 ( _docheck, docheck );
`else
buf ( _docheck, docheck );
`endif
`endif
initial //initialize data flags
begin
docheck = 0;
end
always @( _H01 )
begin
docheck = ( _G099 !== _H01 );
end
always @( posedge _H02 )
begin
docheck = ( _G099 !== _H01 );
end
always @( negedge _H02 )
begin
docheck = ( _G099 !== _H01 );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, negedge H02, DMY_SPC, notifier );
$setup ( negedge H01, negedge H02, DMY_SPC, notifier );
$hold ( negedge H02, posedge H01, DMY_SPC, notifier );
$hold ( negedge H02, negedge H01, DMY_SPC, notifier );
$width ( posedge H02 &&& _docheck, DMY_SPC, 0, notifier );
if ( H02 )
( H01 +=> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H02 )
( H01 -=> N02 ) = ( DMY_SPC, DMY_SPC );
( posedge H02 => ( N01 +: H01 )) = ( DMY_SPC, DMY_SPC );
( posedge H02 => ( N02 -: H01 )) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine