TDADFAX2.v 1.17 KB
// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDADFAX2 ( N01, N02, H01, H02, H03 );
    input H01;
    input H02;
    input H03;
    output N01;
    output N02;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( _H03, H03 );
    xor ( _G001, _H01, _H02 );
    xor ( N01, _G001, _H03 );
    and ( _G002, _H01, _H02 );
    and ( _G003, _H02, _H03 );
    and ( _G004, _H01, _H03 );
    or  ( N02, _G002, _G003, _G004 );

    specify
        specparam DMY_SPC=1;

        ( H01 *> N02 ) = ( DMY_SPC, DMY_SPC );
        ( H02 *> N02 ) = ( DMY_SPC, DMY_SPC );
        ( H03 *> N02 ) = ( DMY_SPC, DMY_SPC );
    if ( H01 )
      ( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
    if ( !H01 )
      ( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
    if ( H02 )
      ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
    if ( !H02 )
      ( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
    if ( H03 )
      ( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
    if ( !H03 )
      ( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine