TDNR3BBY0.v
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// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
// generated by sldtoveri Version 1.3.4
// Mon Jun 19 20:10:16 1995
module TDNR3BBY0 ( N01 , H01 , H02 , H03 ) ;
input H01 ;
input H02 ;
input H03 ;
output N01 ;
buf ( _H01 , H01 ) ;
buf ( _H02 , H02 ) ;
buf ( _H03 , H03 ) ;
not ( C3 , _H02 ) ;
not ( C4 , _H03 ) ;
or ( C2 , _H01 , C3 , C4 ) ;
not ( N01 , C2 ) ;
specify
specparam DMY_SPC=1;
// path from H01 to N01
( H01 *> N01 ) = ( DMY_SPC,
DMY_SPC );
// path from H02 to N01
( H02 *> N01 ) = ( DMY_SPC,
DMY_SPC );
// path from H03 to N01
( H03 *> N01 ) = ( DMY_SPC,
DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine