TDSMDFHQRSBX1U.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSMDFHQRSBX1U ( N01, H01, H02, H03, H04 );
input H01;
input H02;
input H03;
input H04;
output N01;
reg notifier;
reg docheck1;
reg docheck2;
reg docheck3;
reg docheck4;
reg docheck5;
reg docheck6;
reg docheck7;
reg docheck8;
reg docheck9;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( N01, _G007 );
DESFQ ( _G007, _H01, _H02, _H03, _H04, notifier );
buf #1 ( _G099, _G007 );
`ifdef INCA
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
buf #1 ( _docheck7, docheck7 );
buf #1 ( _docheck8, docheck8 );
buf #1 ( _docheck9, docheck9 );
`else
`ifdef VCS
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
buf #1 ( _docheck7, docheck7 );
buf #1 ( _docheck8, docheck8 );
buf #1 ( _docheck9, docheck9 );
`else
buf ( _docheck1, docheck1 );
buf ( _docheck2, docheck2 );
buf ( _docheck3, docheck3 );
buf ( _docheck4, docheck4 );
buf ( _docheck5, docheck5 );
buf ( _docheck6, docheck6 );
buf ( _docheck7, docheck7 );
buf ( _docheck8, docheck8 );
buf ( _docheck9, docheck9 );
`endif
`endif
initial //initialize data flags
begin
docheck1 = 0;
docheck2 = 0;
docheck3 = 0;
docheck4 = 0;
docheck5 = 0;
docheck6 = 0;
docheck7 = 0;
docheck8 = 0;
docheck9 = 0;
end
always @( _H01 or _H03 or _H04 )
begin
docheck1 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0) );
if ( (_H02 === 1'b0) && (_H03 !== 1'b0) && (_H04 !== 1'b0) )
docheck6 = ( _G099 !== _H01 );
if ( (_H02 === 1'b1) && (_H03 !== 1'b0) && (_H04 !== 1'b0) )
docheck7 = ( _G099 !== _H01 );
end
always @( posedge _H02 )
begin
docheck1 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0) );
docheck3 = ( (_H01 !== 1'b0) && (_H04 !== 1'b0) );
docheck5 = ( (_H01 !== 1'b1) && (_H03 !== 1'b0) );
docheck6 = ( (_G099 !== _H01) && (_H03 !== 1'b0) && (_H04 !== 1'b0));
docheck7 = 1;
end
always @( negedge _H02 )
begin
docheck6 = ( (_G099 !== _H01) && (_H03 !== 1'b0) && (_H04 !== 1'b0) );
docheck7 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0) );
end
always @( posedge _H03 )
begin
docheck2 = ( (_H01 !== 1'b0) && (_H04 !== 1'b0) );
docheck8 = ( (_G007 !== 1'b0) && (_H04 !== 1'b0) );
end
always @( negedge _H03 )
begin
docheck8 = ( _H04 !== 1'b0 );
end
always @( _G007 )
begin
if ( (_H03 === 1'b1) && (_H04 !== 1'b0) )
docheck8 = ( _G007 !== 1'b0 );
if ( (_H04 === 1'b1) && (_H03 !== 1'b0) )
docheck9 = ( _G007 !== 1'b1 );
end
always @( posedge _H04 )
begin
docheck4 = ( (_H01 !== 1'b1) && (_H03 !== 1'b0) );
docheck9 = ( (_G007 !== 1'b1) && (_H03 !== 1'b0) );
end
always @( negedge _H04 )
begin
docheck9 = ( _H03 !== 1'b0 );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, posedge H02 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H01, posedge H02 &&& _docheck1, DMY_SPC, notifier );
$hold ( posedge H02, posedge H01 &&& _docheck1, DMY_SPC, notifier );
$hold ( posedge H02, negedge H01 &&& _docheck1, DMY_SPC, notifier );
$setup ( posedge H03, posedge H02 &&& _docheck2, DMY_SPC, notifier );
$hold ( posedge H02, posedge H03 &&& _docheck3, DMY_SPC, notifier );
$setup ( posedge H04, posedge H02 &&& _docheck4, DMY_SPC, notifier );
$hold ( posedge H02, posedge H04 &&& _docheck5, DMY_SPC, notifier );
$width ( posedge H02 &&& _docheck6, DMY_SPC, 0, notifier );
$width ( negedge H02 &&& _docheck7, DMY_SPC, 0, notifier );
$width ( negedge H03 &&& _docheck8, DMY_SPC, 0, notifier );
$width ( negedge H04 &&& _docheck9, DMY_SPC, 0, notifier );
if ( H03 && H04 )
( posedge H02 => ( N01 +: H01 )) = ( DMY_SPC, DMY_SPC );
if ( H04 )
( negedge H03 => ( N01 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( H03 )
( negedge H04 => ( N01 +: 1'b1 )) = ( DMY_SPC, 0:0:0 );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine