// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDSMDFHQX4U ( N01, H01, H02 );
    input H01;
    input H02;
    output N01;
    reg notifier;
    reg docheck1;
    reg docheck2;

    buf ( _H01, H01 );
    buf ( _H02, H02 );
    buf ( N01, _G001 );
    DESFQ ( _G001, _H01, _H02, 1'b1, 1'b1, notifier );
    buf #1 ( _G099, _G001 );

`ifdef  INCA
        buf #1 ( _docheck1, docheck1 );
        buf #1 ( _docheck2, docheck2 );
`else
`ifdef VCS
        buf #1 ( _docheck1, docheck1 );
        buf #1 ( _docheck2, docheck2 );
`else
        buf ( _docheck1, docheck1 );
        buf ( _docheck2, docheck2 );
`endif
`endif

    initial      //initialize data flags
        begin
            docheck1 = 0;
            docheck2 = 0;
        end

    always @( _H01 )
        begin
            if ( _H02 === 1'b0 )
                docheck1 = ( _G099 !== _H01 );
            if ( _H02 === 1'b1 )
                docheck2 = ( _G099 !== _H01 );
          end

    always @( posedge _H02 )
        begin
            docheck1 = ( _G099 !== _H01 );
            docheck2 = 1;
        end

    always @( negedge _H02 )
        begin
            docheck1 = ( _G099 !== _H01 );
        end

    specify
        specparam DMY_SPC=1;

        $setup ( posedge H01, posedge H02, DMY_SPC, notifier );
        $setup ( negedge H01, posedge H02, DMY_SPC, notifier );
        $hold ( posedge H02, posedge H01, DMY_SPC, notifier );
        $hold ( posedge H02, negedge H01, DMY_SPC, notifier );

        $width ( posedge H02 &&& _docheck1, DMY_SPC, 0, notifier );
        $width ( negedge H02 &&& _docheck2, DMY_SPC, 0, notifier );

        ( posedge H02 => ( N01 +: H01 )) = ( DMY_SPC, DMY_SPC );
    endspecify
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine