TDSMDFLQRSBX1U.v
5.03 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSMDFLQRSBX1U ( N01, H01, H02, H03, H04 );
input H01;
input H02;
input H03;
input H04;
output N01;
reg notifier;
reg docheck1;
reg docheck2;
reg docheck3;
reg docheck4;
reg docheck5;
reg docheck6;
reg docheck7;
reg docheck8;
reg docheck9;
buf ( _H01, H01 );
buf ( _H02, H02 );
not ( _G004, _H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( N01, _G007 );
DESFQ ( _G007, _H01, _G004, _H03, _H04, notifier );
buf #1 ( _G099, _G007 );
`ifdef INCA
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
buf #1 ( _docheck7, docheck7 );
buf #1 ( _docheck8, docheck8 );
buf #1 ( _docheck9, docheck9 );
`else
`ifdef VCS
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
buf #1 ( _docheck7, docheck7 );
buf #1 ( _docheck8, docheck8 );
buf #1 ( _docheck9, docheck9 );
`else
buf ( _docheck1, docheck1 );
buf ( _docheck2, docheck2 );
buf ( _docheck3, docheck3 );
buf ( _docheck4, docheck4 );
buf ( _docheck5, docheck5 );
buf ( _docheck6, docheck6 );
buf ( _docheck7, docheck7 );
buf ( _docheck8, docheck8 );
buf ( _docheck9, docheck9 );
`endif
`endif
initial //initialize data flags
begin
docheck1 = 0;
docheck2 = 0;
docheck3 = 0;
docheck4 = 0;
docheck5 = 0;
docheck6 = 0;
docheck7 = 0;
docheck8 = 0;
docheck9 = 0;
end
always @( _H01 or _H03 or _H04 )
begin
docheck1 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0) );
if ( (_H02 === 1'b1) && (_H03 !== 1'b0) && (_H04 !== 1'b0) )
docheck7 = ( _G099 !== _H01 );
if ( (_H02 === 1'b0) && (_H03 !== 1'b0) && (_H04 !== 1'b0) )
docheck6 = ( _G099 !== _H01 );
end
always @( negedge _H02 )
begin
docheck1 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0) );
docheck3 = ( (_H01 !== 1'b0) && (_H04 !== 1'b0) );
docheck5 = ( (_H01 !== 1'b1) && (_H03 !== 1'b0) );
docheck7 = ( (_G099 !== _H01) && (_H03 !== 1'b0) && (_H04 !== 1'b0));
docheck6 = 1;
end
always @( posedge _H02 )
begin
docheck7 = ( (_G099 !== _H01) && (_H03 !== 1'b0) && (_H04 !== 1'b0));
docheck6 = ( (_H03 !== 1'b0) && (_H04 !== 1'b0));
end
always @( posedge _H03 )
begin
docheck2 = ( (_H01 !== 1'b0) && (_H04 !== 1'b0) );
docheck8 = ( (_G007 !== 1'b0) && (_H04 !== 1'b0) );
end
always @( negedge _H03 )
begin
docheck8 = ( _H04 !== 1'b0 );
end
always @( _G007 )
begin
if ( (_H03 === 1'b1) && (_H04 !== 1'b0) )
docheck8 = ( _G007 !== 1'b0 );
if ( (_H04 === 1'b1) && (_H03 !== 1'b0) )
docheck9 = ( _G007 !== 1'b1 );
end
always @( posedge _H04 )
begin
docheck4 = ( (_H01 !== 1'b1) && (_H03 !== 1'b0) );
docheck9 = ( (_G007 !== 1'b1) && (_H03 !== 1'b0) );
end
always @( negedge _H04 )
begin
docheck9 = ( _H03 !== 1'b0 );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, negedge H02 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H01, negedge H02 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H02, posedge H01 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H02, negedge H01 &&& _docheck1, DMY_SPC, notifier );
$setup ( posedge H03, negedge H02 &&& _docheck2, DMY_SPC, notifier );
$hold ( negedge H02, posedge H03 &&& _docheck3, DMY_SPC, notifier );
$setup ( posedge H04, negedge H02 &&& _docheck4, DMY_SPC, notifier );
$hold ( negedge H02, posedge H04 &&& _docheck5, DMY_SPC, notifier );
$width ( posedge H02 &&& _docheck6, DMY_SPC, 0, notifier );
$width ( negedge H02 &&& _docheck7, DMY_SPC, 0, notifier );
$width ( negedge H03 &&& _docheck8, DMY_SPC, 0, notifier );
$width ( negedge H04 &&& _docheck9, DMY_SPC, 0, notifier );
if ( H03 && H04 )
( negedge H02 => ( N01 +: H01 )) = ( DMY_SPC, DMY_SPC );
if ( H04 )
( negedge H03 => ( N01 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( H03 )
( negedge H04 => ( N01 +: 1'b1 )) = ( DMY_SPC, 0:0:0 );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine