// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TBCLH ( N01 ) ;
 output N01 ;

  buf    ( N01 , 1'b1 ) ;
endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine