test.cfg
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# Virsim Configuration File
version "2.2.0"
# Files Open:
# Designator Sources Filename
# ---------- ------- --------
# V1 y /home/berndt/proj/bb/rf/hw/chip/lib/verilog/r4300/tb/verilog.dump.vpd
define exprgroup EGroup0;
define linkwindow A
time 491982000 "1 ps",
exprgroup "EGroup0";
define group "AutoGroup0"
verticalposition 1,
add "V1" "test.sysclk" "strength" 1 ,
add "V1" "test.divmode" "hex" 1 ,
add "V1" "test.pll_lock" "strength" 1 ,
add "V1" "test.coldrst_l" "strength" 1 ,
add "V1" "test.warmrst_l" "strength" 1 ,
add "V1" "test.eok_l" "strength" 1 ,
add "V1" "test.sysad_out" "hex" 1 ,
add "V1" "test.syscmd_out" "binary" 1 ,
add "V1" "test.pvalid_l" "strength" 1 ,
add "V1" "test.sysad_in" "hex" 1 ,
add "V1" "test.syscmd_in" "binary" 1 ,
add "V1" "test.evalid_l" "strength" 1 ,
add "V1" "test.int_l" "binary" 1 ,
add "V1" "test.nmi_l" "strength" 1 ;
define wave
xposition -4,
yposition 43,
width 1241,
height 929,
linkwindow A,
displayinfo 491828324 "1 ps" tpp 559 0,
group "AutoGroup0",
pane1 203,
pane2 125;
define hierarchy
xposition 839,
yposition 0,
width 440,
height 1006,
designator "V1",
layout "default",
topscope "<root>",
pane1 170,
focusscope "<root>",
pane2 212,
locate "scopes",
find "selected",
findtext "*",
pane3 212,
signals on,
ports on,
constants on,
variables on,
generics on,
filtertext "*",
signalscope "test";