// vtestena.v v1 Frank Berndt
// test enable logic;
// :set tabstop=4

`timescale 1ns/1ns

module vtestena (
	sysclk, coldrst_l, v_tread, v_nvout, porst, ena
);
	// operational ports;

	input sysclk;			// system clock;
	input coldrst_l;		// cold reset;
	input v_tread;			// read for test enable;
	input [31:0] v_nvout;	// virage read data;
	input porst;			// sum of power-on resets;
	output ena;				// test enable output;

	// need a flop with async reset, to protect against missing sysclk;
	// enable test mode after read data pattern matches;
	// force enable by not-bonded pad, still need sysclk;

	wire ena_rst;			// sym of async resets;
	wire match;				// enable pattern matches;
	reg ena;				// flop with async clear;
	reg check;				// check virage read data;

	assign ena_rst = ~porst & coldrst_l;
	assign match = (v_nvout == 32'hbb2002fb);

	always @(posedge sysclk)
	begin
		check <= v_tread;
	end

	always @(posedge sysclk or negedge ena_rst)
	begin
		if(ena_rst == 1'b0)
			ena <= 1'b0;
		else if(check)
			ena <= match;
	end

endmodule