csdecode.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphic, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: csdecode.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
/////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: csdecode
// description: Decodes RDP command opcode and outputs control
// signals to latch attributes
//
//
// designer: Mike M. Cai 7/1/94
//
/////////////////////////////////////////////////////////////////////////
module csdecode( // outputs
update_rpt, inc_shf_state,
one_word_cmd, new_prim,
cs_ew_data,
tile_addr, cs_tc_data, we_tile_size, we_tile_attr,
cmd, cmd_size,
start_prim, attr_valid,
// inputs
fifo_out,
texel_size,
shf_state, update_shf,
words_fifo, empty,
rel_sync_tile, rel_sync_pipe, rel_sync_full,
rel_sync_load, copy_fill,
ew_busy, ms_busy, reset_l, gclk);
output update_rpt, inc_shf_state,
one_word_cmd, new_prim;
output [5:0] cmd;
output [4:0] cmd_size;
output [63:0] cs_ew_data;
output [2:0] tile_addr;
output [47:0] cs_tc_data;
output we_tile_size, we_tile_attr;
output start_prim, attr_valid;
input [63:0] fifo_out;
input [1:0] texel_size;
input [4:0] shf_state;
input update_shf;
input [5:0] words_fifo;
input empty;
input rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load;
input copy_fill;
input ew_busy, ms_busy, reset_l, gclk;
reg [5:0] cmd; // piped data from op
reg [4:0] cmd_size;
reg [4:0] delay_state; // piped data from shf_state
reg [63:0] fifo_data; // piped data from fifo_out
wire sync_full, sync_pipe, sync_tile, sync_load; // from sync cmds
wire [4:0] size_prim;
wire new_prim;
wire [63:0] cs_ew_data;
wire [2:0] tile_addr;
wire [47:0] cs_tc_data;
wire we_tile_size, we_tile_attr;
reg sync_tile_state, sync_pipe_state, sync_full_state,
sync_load_state;
wire one_word_cmd;
wire state_zero;
wire start_prim_m;
reg start_prim;
reg attr_valid;
wire sync_none;
wire pipe_busy;
reg stop_wen;
`include "rdpcmd.vh"
// first stage decode to determine what to do nexe
assign pipe_busy = ew_busy | ms_busy;
assign state_zero = shf_state == 5'h0;
cspartdec partial_dec( .sync_tile(sync_tile),
.sync_pipe(sync_pipe),
.sync_full(sync_full),
.sync_load(sync_load),
.one_word_cmd(one_word_cmd),
.size_prim(size_prim),
.fifo_out_cmd(fifo_out[61:56]),
.state_zero(state_zero));
// latch cmd and shf_state
always @(posedge gclk)
begin
cmd <= state_zero ? (fifo_out[61:56] & {6{~empty}}) : (cmd);
cmd_size <= state_zero ? (size_prim) : cmd_size;
start_prim <= state_zero ? start_prim_m : 1'h0;
delay_state <= shf_state;
fifo_data <= fifo_out;
attr_valid <= one_word_cmd & ~pipe_busy & ~empty & sync_none;
stop_wen <= sync_none & ~empty & ~pipe_busy;
end
// state machine for syncing cmd
always @( posedge gclk or negedge reset_l)
if (reset_l == 1'h0) begin
sync_tile_state <= 1'h0;
sync_pipe_state <= 1'h0;
sync_full_state <= 1'h0;
sync_load_state <= 1'h0;
end
else begin
sync_tile_state <= ((~sync_tile_state & sync_tile & ~empty & ~pipe_busy & sync_none) |
(sync_tile_state & ~rel_sync_tile));
sync_pipe_state <= ((~sync_pipe_state & sync_pipe & ~empty & ~pipe_busy & sync_none) |
(sync_pipe_state & ~rel_sync_pipe ));
sync_full_state <= ((~sync_full_state & sync_full & ~empty & ~pipe_busy & sync_none) |
(sync_full_state & ~rel_sync_full));
sync_load_state <= ((~sync_load_state & sync_load & ~empty & ~pipe_busy & sync_none) |
(sync_load_state & ~rel_sync_load));
end
assign sync_none = ~(sync_tile_state | sync_pipe_state | sync_full_state |
sync_load_state);
// determine to update the read pointer
assign update_rpt = ( (one_word_cmd & ~pipe_busy) | update_shf ) &
~empty & sync_none;
// assign inc_shf_state = ~(delay_state == 5'h0) ? 1'h1 :
assign start_prim_m = ((words_fifo >= size_prim) & ~one_word_cmd & ~pipe_busy &
~empty & sync_none );
assign inc_shf_state = (state_zero) ? start_prim_m : 1'h1;
// always @(posedge gclk)
assign new_prim = inc_shf_state;
csdatamux datamux( // outputs
.cs_ew_data(cs_ew_data),
.cs_tc_data(cs_tc_data),
.we_tile_size(we_tile_size),
.we_tile_attr(we_tile_attr),
.tile_addr(tile_addr),
// inputs
.cmd(cmd),
.delay_state(delay_state),
.fifo_data(fifo_data),
.stop_wen(stop_wen),
.texel_size(texel_size),
.copy_fill(copy_fill));
endmodule // csdecode