ep_tc.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ep_tc.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ep_tc
// description: Top level for edge walker pipe.
//
// designer: Phil Gossett
// date: 6/7/95
//
////////////////////////////////////////////////////////////////////////
module ep_tc (gclk, tlut_en, tc_load, ew_st_span, ew_d,
st_span_st_w, st_span_st_s, st_span_st_t,
st_span_tc, st_span_10d,
d_w, d_s, d_t, d_3d);
input gclk;
input tlut_en;
input tc_load;
input ew_st_span;
input [21:0] ew_d;
output st_span_st_w;
output st_span_st_s;
output st_span_st_t;
output st_span_tc;
output st_span_10d;
output [21:0] d_w;
output [21:0] d_s;
output [21:0] d_t;
output [21:0] d_3d;
reg st_span_1d;
reg st_span_2d;
reg st_span_3d;
reg st_span_4d;
reg st_span_5d;
reg st_span_6d;
reg st_span_7d;
reg st_span_8d;
reg st_span_9d;
reg st_span_10d;
reg [21:0] d_1d;
reg [21:0] d_2d;
reg [21:0] d_3d;
reg tc_load_1d;
always @(posedge gclk)
begin
st_span_1d <= ew_st_span;
st_span_2d <= st_span_1d;
st_span_3d <= st_span_2d;
st_span_4d <= st_span_3d;
st_span_5d <= st_span_4d;
st_span_6d <= st_span_5d;
st_span_7d <= st_span_6d;
st_span_8d <= st_span_7d;
st_span_9d <= st_span_8d;
st_span_10d <= st_span_9d;
d_1d <= ew_d;
d_2d <= d_1d;
d_3d <= d_2d;
tc_load_1d <= tc_load;
end
assign st_span_st_w = tlut_en ? st_span_5d : st_span_7d;
assign st_span_st_s = (tlut_en & !tc_load_1d) ? st_span_7d : st_span_9d;
assign st_span_st_t = (tlut_en & !tc_load_1d) ? st_span_7d : st_span_9d;
assign st_span_tc = (tlut_en & !tc_load ) ? st_span_6d : st_span_8d;
assign d_w = tlut_en ? d_1d : d_3d;
assign d_s = (tlut_en & !tc_load_1d) ? d_1d : d_3d;
assign d_t = (tlut_en & !tc_load_1d) ? ew_d : d_2d;
endmodule // ep_tc