/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: ewctr.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
   /////////////////////////////////////////////////////////////////////////
   //
   // Project Reality
   //
   // module:      ewctr
   // description: control module for edge walker
   //
   // designer:    Mike M. Cai  5/11/94
   //
   /////////////////////////////////////////////////////////////////////////
module ewctr(  // outputs
      	       	  prim_busy,
		  ew_cv_newspan, ew_ms_length,
		  ew_ep_startspan, 
		  ld_xmh, ld_dxmdy, ld_dxhdy, ld_dxldy,
		  switch_xl, ld_y, count_y, shift_xval,
		  sel_xval,
		  ld_xmajor, 
		  clear_allxgemax, // clear_allxlessmin is same as clear_allxgemax
		  clear_xminor,
		  ld_a,
		  ra_addr, rb_addr,
		  wa_addr, wde_addr, wen_a, wen_de,
		  add_clear, add32b,
		  shuffle, noshuffle,
		  sel_dydx,
		  ld_x_frac,
		  ew_stall_attr, ew_stall_x,
		  start_mult, addr_newspan,
		  cmp_cross_valid,
      	       	  // inputs
		  x_major, x_sc_max, x_sc_min,
		  allxlmin, allxgemax,
		  end_prim_y, equal_ym, allx_invalid,
      	       	  left_xmajor, left_xminor,
		  sign_dxhdy, //sign_dxmdy, sign_dxldy,
		  cs_ew_newprim, 
		  load_cmd, load_cmd_scissor,
		  load_cmd_tlut,
		  cycle_type, texel_size, pixel_size,
      	       	  sc_field, odd_line, y_cur_lsb, flush,
		  reset_l, gclk);
// outputs
output 	       	  prim_busy;
output	       	  ew_cv_newspan;
output [11:0]  	  ew_ms_length;
output	       	  ew_ep_startspan;
output		  ld_xmh, ld_dxmdy, ld_dxhdy, ld_dxldy;
output		  switch_xl, ld_y, count_y, shift_xval;
output		  sel_xval;
output		  ld_xmajor ;
output		  clear_allxgemax;
output		  clear_xminor;
output		  ld_a;
output [3:0]	  ra_addr, rb_addr;
output [3:0]	  wa_addr, wde_addr;
output	       	  wen_a, wen_de;
output		  add_clear, add32b;
output		  shuffle, noshuffle;
output [3:0]	  sel_dydx;
output		  ld_x_frac;
output		  ew_stall_attr, ew_stall_x;
output	       	  start_mult, addr_newspan;
output	       	  cmp_cross_valid;
// inputs
input [11:0]	  x_major;
input [11:0]	  x_sc_max, x_sc_min;
input		  allxlmin, allxgemax;
input		  end_prim_y, equal_ym, allx_invalid;
input  	       	  left_xmajor, left_xminor; 
input 	       	  sign_dxhdy; // sign_dxmdy, sign_dxldy;
input 	       	  cs_ew_newprim;
input		  load_cmd, load_cmd_scissor;
input 	       	  load_cmd_tlut;
input [1:0]    	  cycle_type, texel_size, pixel_size;
input 	       	  sc_field, odd_line, y_cur_lsb, flush;
input		  reset_l, gclk;

// state machine signals
reg [4:0]      	  cnt_prim;
reg   	       	  rst_cntx, rst_cntattr;
reg [3:0]      	  nxt_cntx, nxt_cntattr;
reg [3:0]      	  cnt_span_x, cnt_span_attr;
wire   	       	  prim_busy;
reg   	       	  span_valid_x;
// general control signals
wire  	       	  span_valid;
reg   	       	  ew_cv_newspan;
reg   	       	  ew_ep_startspan_m, ew_ep_startspan;
// control signals for x's
wire  	       	  ld_xmh, ld_dxmdy, ld_dxhdy, ld_dxldy;
wire  	       	  switch_xl;
wire  	       	  end_x;
// control signals for y's
wire  	       	  ld_y, count_y, shift_xval;
reg  	       	  sel_xval; 
wire  	       	  end_prim; // cancel_span_y;
// control signals for scissoring logic
wire  	       	  ld_xmajor, clear_allxgemax;
reg   	       	  clear_xminor;
// control signals for attributes
wire [3:0]     	  ra_addr, rb_addr;
reg  [3:0]     	  wa_addr_m, wa_addr_s;
wire [3:0]     	  wa_addr;
wire   	       	  ld_a;
reg   	       	  add_clear, add32b;
reg   	       	  shuffle_m, shuffle, noshuffle_m, noshuffle;
reg [3:0]      	  sel_dydx_m, sel_dydx_mm, sel_dydx_mmm, sel_dydx;
reg   	       	  ld_x_frac_m,ld_x_frac_mm;
reg   	       	  ld_x_frac_mmm, ld_x_frac;
wire  	       	  ew_stall_attrb;
reg   	       	  ew_stall_attr;
reg   	       	  ew_stall_attr0d, ew_stall_attr2d, 
   	       	  ew_stall_attr3d, ew_stall_attr4d, ew_stall_attr5d, 
   	       	  ew_stall_attr6d, ew_stall_attr7d, ew_stall_attr8d; 
wire [3:0]     	  wde_addr;
wire  	       	  wen_de, wen_a;
// signals for generating ew_stall_x
reg   	       	  get_new_stall;
wire  	       	  get_ew_stall;
reg [11:0]    	  larger_x, smaller_x, num_pixel;
reg [2:0]      	  num_shift;
reg [3:0]      	  comp_value;
reg [12:0]     	  num_cycles_new, num_cycles;
reg   	       	  ew_stall_x;
wire  	       	  ew_stall_xb;
reg [12:0]     	  stall_decr, cnt_stall;
reg [11:0]     	  ew_ms_length;
reg   	       	  sc_field_s, odd_line_s;       	  
// for address generation
wire	       	  start_mult, addr_newspan;
reg   	       	  end_ew;
reg   	       	  span_valid_s;
reg [1:0]      	  end_prim_state;
reg   	       	  span_valid_x_s;
wire  	       	  cmp_cross_valid;


// State machines including three counters others
always @(posedge gclk or negedge reset_l)
   if (reset_l == 1'h0)
      begin
      	 cnt_prim <= 5'h0;
	 cnt_span_x <= 4'h0;
	 cnt_span_attr <= 4'h0;
//	 ew_busy  <= 1'h0;
	 span_valid_x <= 1'h0;
	 end_ew <= 1'h0;
	 span_valid_s <= 1'h0;
//	 span_valid_attr <= 1'h0;
      end
   else
      begin
      	 if ( cs_ew_newprim & (cnt_prim == 5'h16))
	    cnt_prim <= 5'h1;
	 else
      	    cnt_prim <= (~cs_ew_newprim) ? 5'h0 : 	// cs_ew_newprim is one cycle
	       	     	(cnt_prim + cs_ew_newprim); // earlier than cs_ew_data
	 rst_cntx = (cnt_span_x == 4'h8) | (cnt_prim == 5'h4);
	 nxt_cntx = cnt_span_x + (ew_stall_xb);
      	 cnt_span_x <= rst_cntx ? 4'h0 : nxt_cntx;
      	 rst_cntattr = (cnt_span_attr == 4'h8) | (cnt_prim == 5'hd);
	 nxt_cntattr = cnt_span_attr + (ew_stall_attrb);
	 cnt_span_attr <= rst_cntattr ? 4'h0 : nxt_cntattr;
//	 ew_busy <= (cs_ew_newprim & ~(cnt_prim == 5'h15) & ~(cnt_prim == 5'h14))|
//	       	     (ew_busy & ~(end_prim_y & (cnt_span_x == 4'h6)));
      	 end_ew <= end_prim_y & (cnt_span_x == 4'h8);
	 span_valid_x <= (cnt_prim == 5'h4) | (span_valid_x &
	       	     	   ~(end_prim));
//	 span_valid_attr <= (cnt_prim == 5'hd) | (span_valid_attr &
//	       	     	      ~(end_prim));
	 span_valid_s <= span_valid;
      end

always @(posedge gclk)
   begin
     span_valid_x_s <= span_valid_x;
     sc_field_s	 <= (cnt_prim == 5'hc) ? sc_field : sc_field_s;
     odd_line_s	 <= (cnt_prim == 5'hc) ? odd_line : odd_line_s;
   end

// control signals for detecting edge crossing
assign  cmp_cross_valid = ~cnt_span_x[0] & ~cnt_span_x[3];

// Control signals for generating pixel addresses
assign  start_mult = cnt_prim == 5'h2;
assign  addr_newspan = (cnt_span_x == 4'h8) ;

// General control

assign  span_valid  = 
      	    span_valid_x & ~allx_invalid & ~allxlmin 
      	    & ~allxgemax & ~flush &
	    (~sc_field_s | load_cmd_scissor |
	    (sc_field_s & ~(y_cur_lsb ^ odd_line_s)));

always @(posedge gclk)
   begin
      ew_cv_newspan  <=  (cnt_span_x == 4'h8) & span_valid;
      ew_ep_startspan_m <= ew_cv_newspan;
      ew_ep_startspan <= ew_ep_startspan_m;
   end

// control for x's
assign  ld_xmh = (cnt_prim == 5'h3) | (cnt_prim == 5'h4);
assign  ld_dxmdy = (~(cnt_span_x == 4'h7) & ~ew_stall_x) | ld_xmh;
assign  ld_dxhdy = ld_dxmdy;
assign  ld_dxldy = cnt_prim == 5'h2;
assign  switch_xl = (equal_ym & ~cnt_span_x[0] & ~cnt_span_x[3]) & ~ld_xmh;
assign  end_x = cnt_span_x == 4'h8;

// control for y's
assign  ld_y = cnt_prim == 5'h1;
assign  count_y	 = ((cnt_span_x == 4'h1) | (cnt_span_x == 4'h3) |
      	       	     (cnt_span_x == 4'h5) | (cnt_span_x == 4'h8) ) &
      	       	     ~( (cnt_prim == 5'h1) | (cnt_prim == 5'h2) |
		      (cnt_prim == 5'h3) | (cnt_prim == 5'h4)) &
		      ~ew_stall_x & span_valid_x;
assign  shift_xval   = cnt_span_x[0];
assign  end_prim     = end_prim_y & end_x;


// Scissoring logic
assign  ld_xmajor = (left_xmajor ^ sign_dxhdy) ? 
      	       	     (cnt_span_x == 4'h0) : (cnt_span_x == 4'h6);
// assign  clear_allxlmin = cnt_span_x == 4'h0;
assign  clear_allxgemax 	= cnt_span_x == 4'h0;
always @(posedge gclk)
   begin
      clear_xminor <= ew_stall_x ? clear_xminor : 
      	       	     	(cnt_span_x == 4'h0);
   end

//  ew attribute control
assign  ra_addr	  = cnt_span_attr[3:0];
assign  rb_addr  = cnt_span_attr[3:0];

always @(posedge gclk or negedge reset_l)
   if (reset_l == 1'h0)
      begin
      ew_stall_attr0d <= 1'h0;
      ew_stall_attr2d <= 1'h0;
      ew_stall_attr3d <= 1'h0;
      ew_stall_attr4d <= 1'h0;
      ew_stall_attr5d <= 1'h0;
      ew_stall_attr6d <= 1'h0;
      ew_stall_attr7d <= 1'h0;
      ew_stall_attr8d <= 1'h0;
      ew_stall_attr <= 1'h0;
      sel_xval 	     <= 1'h0;
      end
   else begin
      sel_xval       <= cnt_span_x[3];
      ew_stall_attr0d <= ew_stall_x;
      ew_stall_attr2d <= ew_stall_attr0d;
      ew_stall_attr3d <= ew_stall_attr2d;
      ew_stall_attr4d <= ew_stall_attr3d;
      ew_stall_attr5d <= ew_stall_attr4d;
      ew_stall_attr6d <= ew_stall_attr5d;
      ew_stall_attr7d <= ew_stall_attr6d;
      ew_stall_attr8d <= ew_stall_attr7d;
      ew_stall_attr <= ew_stall_attr8d;
   end

always @(posedge gclk)
   begin
      wa_addr_m      <= ew_stall_attr ? wa_addr_m :cnt_span_attr;
      wa_addr_s      <= ew_stall_attr ? wa_addr_s :wa_addr_m;
      add_clear      <= ew_stall_attr ? add_clear : 
      	       	     	(~cnt_span_attr[0]);
      add32b         <= ew_stall_attr ? add32b : cnt_span_attr[3];
      shuffle_m      <= ew_stall_attr ? shuffle_m : cnt_span_attr[0];
      shuffle        <= shuffle_m;
      noshuffle_m    <= ew_stall_attr ? noshuffle_m : cnt_span_attr[3];
      noshuffle	     <= noshuffle_m;
      sel_dydx_m     <= ew_stall_attr ? sel_dydx_m : cnt_span_attr;
      sel_dydx_mm    <= sel_dydx_m ;
      sel_dydx_mmm   <= sel_dydx_mm;
      sel_dydx       <= sel_dydx_mmm;
      ld_x_frac_m    <= cnt_span_x == 4'h8;
      ld_x_frac_mm   <= ld_x_frac_m;
      ld_x_frac_mmm  <= ld_x_frac_mm;
      ld_x_frac      <= ld_x_frac_mmm;
   end





assign  ew_stall_attrb = ~ew_stall_attr;
/*
assign  ld_a = (cnt_prim[3] & ~cnt_prim[1]) |
      	       	     	   (cnt_prim[3] & ~cnt_prim[2]) |
			   (cnt_prim[2] & ~cnt_prim[1] & cnt_prim[0]) |
			   (~cnt_prim[3] & cnt_prim[2] & cnt_prim[1]);
*/
assign  ld_a   	  = (cnt_prim == 5'h5) | (cnt_prim == 5'h6) |
      	       	    (cnt_prim == 5'h7) | (cnt_prim == 5'h8) | 
      	       	    (cnt_prim == 5'h9) | (cnt_prim == 5'ha) | 
      	       	    (cnt_prim == 5'hb) | (cnt_prim == 5'hc) | 
		    (cnt_prim == 5'hd);		   
assign  wa_addr	  = ld_a ? (cnt_prim - 5'h5) : wa_addr_s;
assign  wde_addr  = cnt_prim - 5'he;
assign  wen_de 	  = (cnt_prim == 5'he) | (cnt_prim == 5'hf) |
      	       	    (cnt_prim == 5'h10) | (cnt_prim == 5'h11) | 
      	       	    (cnt_prim == 5'h12) | (cnt_prim == 5'h13) | 
      	       	    (cnt_prim == 5'h14) | (cnt_prim == 5'h15) | 
		    (cnt_prim == 5'h16);
/* assign  wen_a  	  = ~((cnt_prim == 5'he) | (cnt_prim == 5'hf)) & 
      	       	     (~ew_stall_attr | cs_ew_newprim); */
assign  wen_a  	  = ~((cnt_prim == 5'he) | (cnt_prim == 5'hf)) & 
      	       	     (~ew_stall_attr);
// assign  sel_dx 	  = sel_y;
      	       	    

// ew stall logic
always @ (posedge gclk)
   begin
      get_new_stall <= cnt_span_x[3] & span_valid;
   end
assign  get_ew_stall = get_new_stall | ew_stall_x;

always @ (posedge gclk or negedge reset_l)
if ( reset_l == 0)
   begin
      ew_stall_x <= 1'h0;
      cnt_stall <= 13'h0;
      end_prim_state <= 2'h0;
      ew_ms_length <= 12'h0;
   end
else
   begin
      larger_x = left_xminor ? x_sc_max : x_major;
      smaller_x = left_xminor ? x_major : x_sc_min;
      num_pixel = larger_x - smaller_x;
      ew_ms_length <= num_pixel;
      if ( ~load_cmd)
      	 case (cycle_type)
      	    2'h0: 
	       begin
	       	  num_shift = 3'h0;
		  comp_value = 4'h8;
	       end
	    2'h1: 
	       begin
	       	  num_shift = 3'h1;
		  comp_value = 4'h6;
	       end
	    2'h2: 
	       begin
	       	  num_shift = 3'h2;
		  comp_value = 4'h7;
	       end
	    2'h3:
	       begin
	       	  comp_value = 4'h7;
	       	  case (pixel_size)
	       	     2'h0: num_shift = 3'h4;
		     2'h1: num_shift = 3'h3;
		     2'h2: num_shift = 3'h2;
		     2'h3: num_shift = 3'h1;
	       	  endcase
	       end
	  endcase
      else 
      	 begin
	    if (load_cmd_tlut)
	       begin
      	       	  comp_value = 4'h8;
		  num_shift = 3'b0;
	       end
	    else begin
	       comp_value = 4'h7;
      	       case (texel_size)
	       	  2'h0: num_shift = 3'h4;
	       	  2'h1: num_shift = 3'h3;
	       	  2'h2: num_shift = 3'h2;
	       	  2'h3: num_shift = 3'h1;
	       endcase
	    end
	 end
      if ( ~load_cmd & (cycle_type == 2'h1))
      	 num_cycles_new = num_pixel << num_shift;
      else
      	 num_cycles_new = num_pixel >> num_shift;
      num_cycles  = get_new_stall ? num_cycles_new : cnt_stall;
      ew_stall_x  <= get_ew_stall ? (num_cycles > comp_value) : ew_stall_x;
      // cnt_stall
      stall_decr  = get_new_stall ? (num_cycles_new - 1'h1) : (cnt_stall - 1'h1);
      if ( ew_stall_x | (get_new_stall & ~(num_cycles == 13'b0)))
      	 cnt_stall <= stall_decr;
      else if ( (num_cycles == 13'h0))
      	 cnt_stall <= 13'h0;
      else
      	 cnt_stall <= stall_decr;
//      cnt_stall   <= (ew_stall_x | get_new_stall) ? stall_decr : 
//      	       	  ((cnt_stall <= 13'h0) ? 13'h0 : stall_decr);
      case (end_prim_state)
      	 2'h0:  
	    if (cs_ew_newprim)
	       end_prim_state <= 2'h3;
	    else 
	       end_prim_state <= 2'h0;
	 2'h1:
	    if (cs_ew_newprim)
	       end_prim_state <= 2'h3;
	    else 
	       end_prim_state <= 2'h1;
	 2'h2:
	    if (cnt_stall  == 13'h0)
	       end_prim_state <= 2'h1;
	    else
	       end_prim_state <= 2'h2;
	 2'h3:
	    begin
	       if (cs_ew_newprim & end_ew & span_valid_s & (num_cycles > 13'h8))
	       	  end_prim_state <= 2'h2;
	       else if (cs_ew_newprim)
	       	  end_prim_state <= 2'h3;
	       else if (~span_valid_x_s)
	       	  end_prim_state <= 2'h1;
      	       else if (end_ew & span_valid_s & (num_cycles > 13'h0))
	       	  end_prim_state <= 2'h2;
	       else if (end_ew & ~span_valid_s)
	       	  end_prim_state <=2'h1;
	       else if ( end_ew & (num_cycles == 13'h0))
	       	  end_prim_state <= 2'h1;
	       else 
	       	  end_prim_state <= 2'h3;
	    end
       endcase
   end
assign  ew_stall_xb = ~ew_stall_x;      
assign  prim_busy = end_prim_state[1];
           
endmodule  //  ewctr