pi.v
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/************************************************************************\
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
\************************************************************************/
// $Id: pi.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
`timescale 1ns / 1ns
module pi(clock, reset_l,
cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
dma_start, dma_last, dbus_enable, dma_grant, read_grant, ad16_data_in,
dma_request, read_request, pi_interrupt, ad16_aleh, ad16_alel,
ad16_read_l, ad16_write_l, ad16_enable_l, ad16_data_out,
cbus_data, dbus_data);
`include "pi.vh"
input clock; // system clock
input reset_l; // system reset_l
input cbus_read_enable; // enable cbus read mux
input cbus_write_enable; // enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select; // cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command; // cbus data type
input dma_start; // first dbus word flag
input dma_last; // last dbus word flag
input dbus_enable; // enable dbus tristate drivers
input dma_grant; // DMA request granted
input read_grant; // read request granted
input [AD16_DATA_SIZE-1:0] ad16_data_in; // AD 16 input data
output dma_request; // request a DMA cycle
output read_request; // request a read response cycle
output pi_interrupt; // DMA cycle in progress
output ad16_aleh;
output ad16_alel;
output ad16_read_l;
output ad16_write_l;
output ad16_enable_l;
output [AD16_DATA_SIZE-1:0] ad16_data_out;
inout [CBUS_DATA_SIZE-1:0] cbus_data; // IO bus
inout [DBUS_DATA_SIZE-1:0] dbus_data; // DMA bus
wire dma_read;
wire [DRAM_ADDRESS_SIZE-1:0] dma_address;
wire [DMA_LENGTH_SIZE-1:0] dma_length;
wire [CBUS_DATA_SIZE-1:0] reg_read_data;
wire [CBUS_DATA_SIZE-1:0] reg_write_data;
wire [PI_REG_ADDRESS_SIZE-1:0] reg_address;
wire [CBUS_DATA_SIZE-1:0] io_address;
wire reg_write_enable;
wire io_busy;
wire iobuf_write_enable;
wire [IOBUF_ADDRESS_SIZE-1:0] iobuf_address;
wire [IOBUF_DATA_SIZE-1:0] iobuf_data_in;
wire [IOBUF_DATA_SIZE-1:0] iobuf_data_out;
pi_dma pi_dma_0(
.clock( clock),
.reset_l( reset_l),
.cbus_read_enable( cbus_read_enable),
.cbus_write_enable( cbus_write_enable),
.cbus_select( cbus_select),
.cbus_command( cbus_command),
.read_grant( read_grant),
.dma_read( dma_read),
.dma_address( dma_address),
.dma_length( dma_length),
.reg_read_data( reg_read_data),
.io_busy( io_busy),
.read_request( read_request),
.reg_write_data( reg_write_data),
.reg_address( reg_address),
.io_address( io_address),
.reg_write_enable( reg_write_enable),
.cbus_data( cbus_data));
pi_controller pi_controller_0(
.clock( clock),
.reset_l( reset_l),
.osr_pic_intr( pi_interrupt),
.osr_io_busy( io_busy),
.icw_dma_grant( dma_grant),
.icw_dma_start( dma_start),
.icw_dma_last( dma_last),
.ocr_dma_req( dma_request),
.ocr_dma_read( dma_read),
.ocr_dma_len( dma_length),
.oar_dma_addr( dma_address),
.icw_reg_wenb( reg_write_enable),
.icw_reg_addr( reg_address),
.iaw_ioc_addr( io_address),
.idw_reg_wdata( reg_write_data),
.odw_reg_rdata( reg_read_data),
.osr_adb_aleh( ad16_aleh),
.osr_adb_alel( ad16_alel),
.osr_adb_rd_l( ad16_read_l),
.osr_adb_wr_l( ad16_write_l),
.idw_adb_din( ad16_data_in),
.ocr_adb_oenb_l( ad16_enable_l),
.odr_adb_dout( ad16_data_out),
.ocr_buf_wenb( iobuf_write_enable),
.oaw_buf_addr( iobuf_address),
.odr_buf_din( iobuf_data_in),
.idw_buf_dout( iobuf_data_out),
.icw_dbu_oenb( dbus_enable),
.tbw_dbu_data( dbus_data));
iobuf pi_iobuf_0(.wen(iobuf_write_enable), .clk(clock),
.a(iobuf_address), .di(iobuf_data_in),
.dout(iobuf_data_out));
endmodule