/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: rspbusses.v,v 1.1 2002/03/28 00:26:13 berndt Exp $

// rspbusses.v		interface between imem/dmem and outside world.

`timescale 1ns / 10ps

module rspbusses (clk, reset_l, iddq_test, 
 	cbus_write_enable, dbus_read_enable, dbus_write_enable, 
	io_load, io_read_select, io_write_select, 
	dma_imem_select, xbus_dmem_select, 
	dma_dm_to_rd, dma_rd_to_dm, dma_address, dma_mask,mem_load,  
	im_to_rd_data, dmem_rd_data, 
	pc, final_pc, imem_web, imem_dma_cycle, 
	bist_go, bist_check, 
	cbus_data, dbus_data, xbus_data,
	ex_dma_rd_to_dm, ex_dma_dm_to_rd,  
	mem_write_data, imem_datain, 
 	dma_wen, imem_csb, bist_done, bist_fail, debug_pc);

    input		clk;
    input		reset_l;
    input		iddq_test;

    // DMA interface signals

    input 		cbus_write_enable;
    input 		dbus_read_enable;	// mess with dbus data
    input 		dbus_write_enable;	// enable dbus drivers
    input 		io_load;		// load cbus reg from cbus
    input		io_read_select;
    input		io_write_select;
    input		dma_imem_select;	// DMA is for IMem, not DMem
    input 		xbus_dmem_select;
    input 		dma_dm_to_rd;		// RD: enable dma write
    input 		dma_rd_to_dm;		// RD: enable dma read
    input	[11:3]	dma_address;
    input 	[1:0] 	dma_mask;		// 32-bit word  write enable
    input		mem_load;		// load cbus reg from imem/dmem
    input	[63:0]	im_to_rd_data;		// dma data from imem
    input 	[63:0] 	dmem_rd_data;

    input	[11:2]	pc;
    input		imem_dma_cycle;

    input		bist_go;
    input		bist_check;

    inout 	[31:0] 	cbus_data;
    inout 	[63:0] 	dbus_data;		// DMA bus

    output	[63:0]	xbus_data;
    output 		ex_dma_rd_to_dm;
    output 		ex_dma_dm_to_rd;
    output 	[63:0] 	mem_write_data;
    output	[63:0]	imem_datain;
    output	[3:0]	dma_wen;

    output	[11:3]	final_pc;
    output		imem_web;
    output		imem_csb;
    output		bist_done;
    output	[3:0]	bist_fail;
    output	[11:0]	debug_pc;		// for debug only

rspbusses_inner rspbusses_inner(clk, reset_l, iddq_test, 
 	cbus_write_enable, dbus_read_enable, dbus_write_enable, 
	io_load, io_read_select, io_write_select, 
	dma_imem_select, xbus_dmem_select, 
	dma_dm_to_rd, dma_rd_to_dm, dma_address, dma_mask,mem_load,  
	im_to_rd_data, dmem_rd_data, 
	pc, final_pc, imem_web, imem_dma_cycle, 
	bist_go, bist_check, 
	cbus_data, cbus_data, dbus_data, dbus_data, xbus_data,
	ex_dma_rd_to_dm, ex_dma_dm_to_rd,  
	mem_write_data, imem_datain, 
 	dma_wen, imem_csb, bist_done, bist_fail, debug_pc);

endmodule


module rspbusses_inner (clk, reset_l, iddq_test, 
 	cbus_write_enable, dbus_read_enable, dbus_write_enable, 
	io_load, io_read_select, io_write_select, 
	dma_imem_select, xbus_dmem_select, 
	dma_dm_to_rd, dma_rd_to_dm, dma_address, dma_mask,mem_load,  
	im_to_rd_data, dmem_rd_data, 
	pc, final_pc, imem_web, imem_dma_cycle, 
	bist_go, bist_check, 
	cbus_data_in, cbus_data_out, dbus_data_in, dbus_data_out, xbus_data,
	ex_dma_rd_to_dm, ex_dma_dm_to_rd,  
	mem_write_data, imem_datain, 
 	dma_wen, imem_csb, bist_done, bist_fail, debug_pc);

    input		clk;
    input		reset_l;
    input		iddq_test;

    // DMA interface signals

    input 		cbus_write_enable;
    input 		dbus_read_enable;	// mess with dbus data
    input 		dbus_write_enable;	// enable dbus drivers
    input 		io_load;		// load cbus reg from cbus
    input		io_read_select;
    input		io_write_select;
    input		dma_imem_select;	// DMA is for IMem, not DMem
    input 		xbus_dmem_select;
    input 		dma_dm_to_rd;		// RD: enable dma write
    input 		dma_rd_to_dm;		// RD: enable dma read
    input	[11:3]	dma_address;
    input 	[1:0] 	dma_mask;		// 32-bit word  write enable
    input		mem_load;		// load cbus reg from imem/dmem
    input	[63:0]	im_to_rd_data;		// dma data from imem
    input 	[63:0] 	dmem_rd_data;

    input	[11:2]	pc;
    input		imem_dma_cycle;

    input		bist_go;
    input		bist_check;

    input 	[31:0] 	cbus_data_in;
    output 	[31:0] 	cbus_data_out;
    input 	[63:0] 	dbus_data_in;		// DMA bus
    output 	[63:0] 	dbus_data_out;		// DMA bus

    output	[63:0]	xbus_data;
    output 		ex_dma_rd_to_dm;
    output 		ex_dma_dm_to_rd;
    output 	[63:0] 	mem_write_data;
    output	[63:0]	imem_datain;
    output	[3:0]	dma_wen;

    output	[11:3]	final_pc;
    output		imem_web;
    output		imem_csb;
    output		bist_done;
    output	[3:0]	bist_fail;
    output	[11:0]	debug_pc;		// for debug only

    wire		reset_l_lat;
    wire		im_to_rd_pre_pre_if;
    wire		im_to_rd_pre_if;
    wire		im_to_rd_if;
    wire		im_to_rd_rd;
    wire 		rd_to_im_pre_if;
    wire		rd_to_im_pre_pre_if;
    wire		rd_to_im_if;
    wire 	[11:3] 	imem_dma_address;	// IF stage

    wire	[1:0]	dma_mask_pl;
    wire		dma_rd_to_dm_d;
    wire		ex_dma_rd_to_dm;
    wire 		dma_dm_to_rd_d;
    wire 	[63:0] 	next_dbus_data;
    wire 	[63:0] 	dbus_data_reg;
    wire 	[63:0] 	mem_read_data;
    wire 	[63:0] 	mem_write_data_tmp;
    wire	[63:0]	mem_write_data_delayed;
    wire 	[63:0] 	rd_to_im_data;

    wire 	[31:0] 	io_read_data;
    wire 	[31:0] 	mem_load_data;
    wire 	[63:0] 	io_write_data;
    wire 	[31:0] 	next_cbus_data;
    wire 	[31:0] 	cbus_data_reg;


asdff #(1,0) sb_reset_ff (reset_l_lat, reset_l, clk, 1'b1);

// ******************* DMA Interface Logic *************************

assign im_to_rd_pre_pre_if = dma_dm_to_rd && dma_imem_select;
asdff #(1,0) rsp_ppipi_imtordff (im_to_rd_pre_if,im_to_rd_pre_pre_if,clk,reset_l);
asdff #(1,0) rsp_piif_im_to_rd_ff (im_to_rd_if,im_to_rd_pre_if,clk,reset_l);
asdff #(1,0) rsp_ir_im_to_rd_ff (im_to_rd_rd,im_to_rd_if,clk,reset_l);
	
asdff  #(2,0) rsp_dma_mask_ff (dma_mask_pl, dma_mask, clk, reset_l);
assign dma_wen = {4{ex_dma_rd_to_dm}} & {dma_mask_pl, dma_mask};

assign dma_rd_to_dm_d = dma_rd_to_dm && !dma_imem_select;
assign dma_dm_to_rd_d = dma_dm_to_rd && !dma_imem_select;
asdff #(1,0) rsp_re_rd_to_dm_ff (ex_dma_rd_to_dm, dma_rd_to_dm_d, clk,reset_l);
asdff #(1,0) rsp_re_dm_to_rd_ff (ex_dma_dm_to_rd, dma_dm_to_rd_d, clk,reset_l);

// DMem to RDP
assign xbus_data = xbus_dmem_select ? dmem_rd_data : dbus_data_reg;

// IMem to CBUS

assign rd_to_im_pre_pre_if = dma_rd_to_dm && dma_imem_select;
asdff #(1,0) rsp_ppipi_rdtoifff (rd_to_im_pre_if,rd_to_im_pre_pre_if,clk,reset_l);
asdff #(1,0) rsp_piif_rdtoifff (rd_to_im_if, rd_to_im_pre_if, clk, reset_l);
asdff #(64,0) dma_wr_data_ff (mem_write_data_delayed, mem_write_data, clk, reset_l);
asdffen #(64,0) dma_imem_wr_ff (rd_to_im_data, mem_write_data_delayed, rd_to_im_pre_if, clk, reset_l);
asdff #(9,0) dma_im_addr_ff (imem_dma_address, dma_address ,clk, reset_l);

// DBus interface

mx21d2_64 mem_rd_mx (dmem_rd_data, im_to_rd_data, im_to_rd_rd, mem_read_data);
assign next_dbus_data = dbus_read_enable ? dbus_data_in : mem_read_data;
asdff #(64,0) rsp_dma_dbus_in_ff (dbus_data_reg, next_dbus_data,clk,reset_l);

dbus_driver dbus_driver_ls(
   .dbus_data_out(dbus_data_reg),
   .dbus_enable(dbus_write_enable),
   .dbus_data(dbus_data_out));

// CBus interface

assign io_read_data = io_read_select ? mem_read_data[31:0] : mem_read_data[63:32];
assign mem_load_data = mem_load ? io_read_data : cbus_data_reg;
assign next_cbus_data = io_load ? cbus_data_in : mem_load_data;
asdff #(32, 0) dma_cbus_ff (cbus_data_reg, next_cbus_data, clk, reset_l);
cbus_driver cbus_driver_ls(
   .cbus_data_out(cbus_data_reg),
   .cbus_enable(cbus_write_enable),
   .cbus_data(cbus_data_out));
mx21d2_64 io_wr_mx ({cbus_data_reg, mem_read_data[31:0]}, 
   {mem_read_data[63:32], cbus_data_reg}, io_read_select, io_write_data);
mx21d2_64 mem_wr_mx (dbus_data_reg, io_write_data, io_write_select, 
   mem_write_data_tmp);

ni01d7_64 mem_wr_drv (mem_write_data_tmp, mem_write_data);

// BIST

ram_bist_imem ram_bist_imem (
	.clk		(clk),
	.reset_l	(reset_l),
	.iddq_test	(iddq_test),
	.bist_go	(bist_go),
	.bist_check	(bist_check),

	.sys_addr	(pc[11:3]),
	.sys_din	(rd_to_im_data),
	.dma_addr	(imem_dma_address),
	.dma_cycle	(imem_dma_cycle),
	.sys_web	(!(rd_to_im_if || !reset_l_lat)),
	.sys_csb	(1'b0),
	.ram_do		(im_to_rd_data),
	.ram_addr	(final_pc),
	.ram_din	(imem_datain),
	.ram_web	(imem_web),
	.ram_csb	(imem_csb),

	.bist_done	(bist_done),
	.bist3_fail	(bist_fail[3]),
	.bist2_fail	(bist_fail[2]),
	.bist1_fail	(bist_fail[1]),
	.bist0_fail	(bist_fail[0])
);

assign debug_pc = {final_pc, 3'b0};

endmodule

module mx21d2_64 (i0, i1, s, z);

input [63:0] i0;
input [63:0] i1;
input s;
output [63:0] z;

wire s0, s1;
wire sa0, sb0, sc0, sd0;
wire sa1, sb1, sc1, sd1;

ni01d4 u_s0_2(.z(s0), .i(s));
ni01d4 u_s1_2(.z(s1), .i(s));

ni01d5 u_sa0_2(.z(sa0), .i(s0));
ni01d5 u_sb0_2(.z(sb0), .i(s0));
ni01d5 u_sc0_2(.z(sc0), .i(s0));
ni01d5 u_sd0_2(.z(sd0), .i(s0));

ni01d5 u_sa1_2(.z(sa1), .i(s1));
ni01d5 u_sb1_2(.z(sb1), .i(s1));
ni01d5 u_sc1_2(.z(sc1), .i(s1));
ni01d5 u_sd1_2(.z(sd1), .i(s1));

mx21d2 u_00(.z(z[ 0]), .i0(i0[ 0]), .i1(i1[ 0]), .s(sa0));
mx21d2 u_01(.z(z[ 1]), .i0(i0[ 1]), .i1(i1[ 1]), .s(sa0));
mx21d2 u_02(.z(z[ 2]), .i0(i0[ 2]), .i1(i1[ 2]), .s(sa0));
mx21d2 u_03(.z(z[ 3]), .i0(i0[ 3]), .i1(i1[ 3]), .s(sa0));
mx21d2 u_04(.z(z[ 4]), .i0(i0[ 4]), .i1(i1[ 4]), .s(sa0));
mx21d2 u_05(.z(z[ 5]), .i0(i0[ 5]), .i1(i1[ 5]), .s(sa0));
mx21d2 u_06(.z(z[ 6]), .i0(i0[ 6]), .i1(i1[ 6]), .s(sa0));
mx21d2 u_07(.z(z[ 7]), .i0(i0[ 7]), .i1(i1[ 7]), .s(sa0));

mx21d2 u_08(.z(z[ 8]), .i0(i0[ 8]), .i1(i1[ 8]), .s(sb0));
mx21d2 u_09(.z(z[ 9]), .i0(i0[ 9]), .i1(i1[ 9]), .s(sb0));
mx21d2 u_10(.z(z[10]), .i0(i0[10]), .i1(i1[10]), .s(sb0));
mx21d2 u_11(.z(z[11]), .i0(i0[11]), .i1(i1[11]), .s(sb0));
mx21d2 u_12(.z(z[12]), .i0(i0[12]), .i1(i1[12]), .s(sb0));
mx21d2 u_13(.z(z[13]), .i0(i0[13]), .i1(i1[13]), .s(sb0));
mx21d2 u_14(.z(z[14]), .i0(i0[14]), .i1(i1[14]), .s(sb0));
mx21d2 u_15(.z(z[15]), .i0(i0[15]), .i1(i1[15]), .s(sb0));

mx21d2 u_16(.z(z[16]), .i0(i0[16]), .i1(i1[16]), .s(sc0));
mx21d2 u_17(.z(z[17]), .i0(i0[17]), .i1(i1[17]), .s(sc0));
mx21d2 u_18(.z(z[18]), .i0(i0[18]), .i1(i1[18]), .s(sc0));
mx21d2 u_19(.z(z[19]), .i0(i0[19]), .i1(i1[19]), .s(sc0));
mx21d2 u_20(.z(z[20]), .i0(i0[20]), .i1(i1[20]), .s(sc0));
mx21d2 u_21(.z(z[21]), .i0(i0[21]), .i1(i1[21]), .s(sc0));
mx21d2 u_22(.z(z[22]), .i0(i0[22]), .i1(i1[22]), .s(sc0));
mx21d2 u_23(.z(z[23]), .i0(i0[23]), .i1(i1[23]), .s(sc0));

mx21d2 u_24(.z(z[24]), .i0(i0[24]), .i1(i1[24]), .s(sd0));
mx21d2 u_25(.z(z[25]), .i0(i0[25]), .i1(i1[25]), .s(sd0));
mx21d2 u_26(.z(z[26]), .i0(i0[26]), .i1(i1[26]), .s(sd0));
mx21d2 u_27(.z(z[27]), .i0(i0[27]), .i1(i1[27]), .s(sd0));
mx21d2 u_28(.z(z[28]), .i0(i0[28]), .i1(i1[28]), .s(sd0));
mx21d2 u_29(.z(z[29]), .i0(i0[29]), .i1(i1[29]), .s(sd0));
mx21d2 u_30(.z(z[30]), .i0(i0[30]), .i1(i1[30]), .s(sd0));
mx21d2 u_31(.z(z[31]), .i0(i0[31]), .i1(i1[31]), .s(sd0));

mx21d2 u_32(.z(z[32]), .i0(i0[32]), .i1(i1[32]), .s(sa1));
mx21d2 u_33(.z(z[33]), .i0(i0[33]), .i1(i1[33]), .s(sa1));
mx21d2 u_34(.z(z[34]), .i0(i0[34]), .i1(i1[34]), .s(sa1));
mx21d2 u_35(.z(z[35]), .i0(i0[35]), .i1(i1[35]), .s(sa1));
mx21d2 u_36(.z(z[36]), .i0(i0[36]), .i1(i1[36]), .s(sa1));
mx21d2 u_37(.z(z[37]), .i0(i0[37]), .i1(i1[37]), .s(sa1));
mx21d2 u_38(.z(z[38]), .i0(i0[38]), .i1(i1[38]), .s(sa1));
mx21d2 u_39(.z(z[39]), .i0(i0[39]), .i1(i1[39]), .s(sa1));

mx21d2 u_40(.z(z[40]), .i0(i0[40]), .i1(i1[40]), .s(sb1));
mx21d2 u_41(.z(z[41]), .i0(i0[41]), .i1(i1[41]), .s(sb1));
mx21d2 u_42(.z(z[42]), .i0(i0[42]), .i1(i1[42]), .s(sb1));
mx21d2 u_43(.z(z[43]), .i0(i0[43]), .i1(i1[43]), .s(sb1));
mx21d2 u_44(.z(z[44]), .i0(i0[44]), .i1(i1[44]), .s(sb1));
mx21d2 u_45(.z(z[45]), .i0(i0[45]), .i1(i1[45]), .s(sb1));
mx21d2 u_46(.z(z[46]), .i0(i0[46]), .i1(i1[46]), .s(sb1));
mx21d2 u_47(.z(z[47]), .i0(i0[47]), .i1(i1[47]), .s(sb1));

mx21d2 u_48(.z(z[48]), .i0(i0[48]), .i1(i1[48]), .s(sc1));
mx21d2 u_49(.z(z[49]), .i0(i0[49]), .i1(i1[49]), .s(sc1));
mx21d2 u_50(.z(z[50]), .i0(i0[50]), .i1(i1[50]), .s(sc1));
mx21d2 u_51(.z(z[51]), .i0(i0[51]), .i1(i1[51]), .s(sc1));
mx21d2 u_52(.z(z[52]), .i0(i0[52]), .i1(i1[52]), .s(sc1));
mx21d2 u_53(.z(z[53]), .i0(i0[53]), .i1(i1[53]), .s(sc1));
mx21d2 u_54(.z(z[54]), .i0(i0[54]), .i1(i1[54]), .s(sc1));
mx21d2 u_55(.z(z[55]), .i0(i0[55]), .i1(i1[55]), .s(sc1));

mx21d2 u_56(.z(z[56]), .i0(i0[56]), .i1(i1[56]), .s(sd1));
mx21d2 u_57(.z(z[57]), .i0(i0[57]), .i1(i1[57]), .s(sd1));
mx21d2 u_58(.z(z[58]), .i0(i0[58]), .i1(i1[58]), .s(sd1));
mx21d2 u_59(.z(z[59]), .i0(i0[59]), .i1(i1[59]), .s(sd1));
mx21d2 u_60(.z(z[60]), .i0(i0[60]), .i1(i1[60]), .s(sd1));
mx21d2 u_61(.z(z[61]), .i0(i0[61]), .i1(i1[61]), .s(sd1));
mx21d2 u_62(.z(z[62]), .i0(i0[62]), .i1(i1[62]), .s(sd1));
mx21d2 u_63(.z(z[63]), .i0(i0[63]), .i1(i1[63]), .s(sd1));

endmodule


module ni01d7_64 (i, z);

input [63:0] i;
output [63:0] z;

ni01d7 ni_00(.z(z[ 0]), .i(i[ 0]));
ni01d7 ni_01(.z(z[ 1]), .i(i[ 1]));
ni01d7 ni_02(.z(z[ 2]), .i(i[ 2]));
ni01d7 ni_03(.z(z[ 3]), .i(i[ 3]));
ni01d7 ni_04(.z(z[ 4]), .i(i[ 4]));
ni01d7 ni_05(.z(z[ 5]), .i(i[ 5]));
ni01d7 ni_06(.z(z[ 6]), .i(i[ 6]));
ni01d7 ni_07(.z(z[ 7]), .i(i[ 7]));

ni01d7 ni_08(.z(z[ 8]), .i(i[ 8]));
ni01d7 ni_09(.z(z[ 9]), .i(i[ 9]));
ni01d7 ni_10(.z(z[10]), .i(i[10]));
ni01d7 ni_11(.z(z[11]), .i(i[11]));
ni01d7 ni_12(.z(z[12]), .i(i[12]));
ni01d7 ni_13(.z(z[13]), .i(i[13]));
ni01d7 ni_14(.z(z[14]), .i(i[14]));
ni01d7 ni_15(.z(z[15]), .i(i[15]));

ni01d7 ni_16(.z(z[16]), .i(i[16]));
ni01d7 ni_17(.z(z[17]), .i(i[17]));
ni01d7 ni_18(.z(z[18]), .i(i[18]));
ni01d7 ni_19(.z(z[19]), .i(i[19]));
ni01d7 ni_20(.z(z[20]), .i(i[20]));
ni01d7 ni_21(.z(z[21]), .i(i[21]));
ni01d7 ni_22(.z(z[22]), .i(i[22]));
ni01d7 ni_23(.z(z[23]), .i(i[23]));

ni01d7 ni_24(.z(z[24]), .i(i[24]));
ni01d7 ni_25(.z(z[25]), .i(i[25]));
ni01d7 ni_26(.z(z[26]), .i(i[26]));
ni01d7 ni_27(.z(z[27]), .i(i[27]));
ni01d7 ni_28(.z(z[28]), .i(i[28]));
ni01d7 ni_29(.z(z[29]), .i(i[29]));
ni01d7 ni_30(.z(z[30]), .i(i[30]));
ni01d7 ni_31(.z(z[31]), .i(i[31]));

ni01d7 ni_32(.z(z[32]), .i(i[32]));
ni01d7 ni_33(.z(z[33]), .i(i[33]));
ni01d7 ni_34(.z(z[34]), .i(i[34]));
ni01d7 ni_35(.z(z[35]), .i(i[35]));
ni01d7 ni_36(.z(z[36]), .i(i[36]));
ni01d7 ni_37(.z(z[37]), .i(i[37]));
ni01d7 ni_38(.z(z[38]), .i(i[38]));
ni01d7 ni_39(.z(z[39]), .i(i[39]));

ni01d7 ni_40(.z(z[40]), .i(i[40]));
ni01d7 ni_41(.z(z[41]), .i(i[41]));
ni01d7 ni_42(.z(z[42]), .i(i[42]));
ni01d7 ni_43(.z(z[43]), .i(i[43]));
ni01d7 ni_44(.z(z[44]), .i(i[44]));
ni01d7 ni_45(.z(z[45]), .i(i[45]));
ni01d7 ni_46(.z(z[46]), .i(i[46]));
ni01d7 ni_47(.z(z[47]), .i(i[47]));

ni01d7 ni_48(.z(z[48]), .i(i[48]));
ni01d7 ni_49(.z(z[49]), .i(i[49]));
ni01d7 ni_50(.z(z[50]), .i(i[50]));
ni01d7 ni_51(.z(z[51]), .i(i[51]));
ni01d7 ni_52(.z(z[52]), .i(i[52]));
ni01d7 ni_53(.z(z[53]), .i(i[53]));
ni01d7 ni_54(.z(z[54]), .i(i[54]));
ni01d7 ni_55(.z(z[55]), .i(i[55]));

ni01d7 ni_56(.z(z[56]), .i(i[56]));
ni01d7 ni_57(.z(z[57]), .i(i[57]));
ni01d7 ni_58(.z(z[58]), .i(i[58]));
ni01d7 ni_59(.z(z[59]), .i(i[59]));
ni01d7 ni_60(.z(z[60]), .i(i[60]));
ni01d7 ni_61(.z(z[61]), .i(i[61]));
ni01d7 ni_62(.z(z[62]), .i(i[62]));
ni01d7 ni_63(.z(z[63]), .i(i[63]));

endmodule