ststwl.v 1.98 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: ststwl.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
/*      Project Reality
        MDP
        Created by Mike M. Cai  5/25/94
*/

module ststwl(	  att_data_out, 
      	       	  att_data_in, dx, dy,
		  left_major, load, ncyc, gclk);
output [15:0]  att_data_out;
input [26:0]   att_data_in, dx;
input [16:0]   dy;
input 	       left_major, load, ncyc, gclk;

wire [26:0]    att_accum, dx_dir, dx_dir_m;
reg [26:0]     att_cur_s, att_cur_m;
wire [15:0]    att_data_out;
reg [15:0]     att_dy_out;
reg   	       comp_new;

always @(posedge gclk)
   begin
      att_cur_m = load ? att_data_in : att_accum;
      att_cur_s <= (comp_new | load) ? att_cur_m : att_cur_s;
      comp_new <= load ? ~ncyc : (ncyc ? ~comp_new : comp_new);
      att_dy_out <= att_accum[26:11];
   end
assign  dx_dir_m = (dx ~^ {27{left_major}}) & {27{comp_new}};
assign  dx_dir = comp_new ? dx_dir_m : {dy, 10'b0};
      
adder27b adder ( .sum(att_accum), .a(att_cur_s), .b(dx_dir), 
      	       	  .ci(~left_major & comp_new));

// assign  att_data_out = (comp_new & ncyc) ? att_cur_s[26:11] : att_dy_out ;
assign  att_data_out = (comp_new & ncyc) ? att_dy_out : att_cur_s[26:11];

endmodule  //  ststwl