tm_load.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tm_load.v,v 1.1 2002/03/28 00:26:14 berndt Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tm_load
// description: texture memory load interface
//
// designer: Tony DeLaurier
// date: 8/3/94
//
////////////////////////////////////////////////////////////////////////
module tm_load (gclk, copy_load, load_dv, tile_tex_type, tile_tex_size,
odd_t, a_three, a_twelve, di_high, di_low, web01_low,
web23_low, web01_high, web23_high);
`include "tex.vh"
input gclk; // RDP gated clock
input [63:0] copy_load; // copy / load bus
input load_dv; // valid load data on copy_load bus
input [2:0] tile_tex_type; // tile texel type
input [1:0] tile_tex_size; // tile texel size
input odd_t; // odd line
input a_three; // address a[3] before interleave
input a_twelve; // address a[12]
output [63:0] di_high; // data_in to high banks
output [63:0] di_low; // data_in to low banks
output web01_low; // write enable banks 0,1 (low half)
reg web01_low; // write enable banks 0,1 (low half)
output web23_low; // write enable banks 2,3 (low half)
reg web23_low; // write enable banks 2,3 (low half)
output web01_high; // write enable banks 0,1 (high half)
reg web01_high; // write enable banks 0,1 (high half)
output web23_high; // write enable banks 2,3 (high half)
reg web23_high; // write enable banks 2,3 (high half)
reg [63:0] copy_load_1d; // copy_load delayed 1
reg [1:0] sel; // data in mux selects
reg yuv_16b; // tile type is 16 bit yuv
reg rgba_32b; // tile type is 32 bit rgba
// 4 to 1 mux function
function [63:0] four_to_one;
input [1:0] sel;
input [63:0] in_zero;
input [63:0] in_one;
input [63:0] in_two;
input [63:0] in_three;
begin
case (sel[1:0])
2'b00: four_to_one = in_zero;
2'b01: four_to_one = in_one;
2'b10: four_to_one = in_two;
2'b11: four_to_one = in_three;
default: four_to_one = 64'hx;
endcase
end
endfunction // four_to_one
always @(posedge gclk)
begin
// delay copy_load bus by 1 clock
copy_load_1d <= copy_load;
// determine mux selects
yuv_16b = (tile_tex_type == TYPE_YUV);
rgba_32b = ((tile_tex_type == TYPE_RGBA) && (tile_tex_size == SIZE_32BIT));
sel[1] <= rgba_32b || yuv_16b;
sel[0] <= (!rgba_32b && !yuv_16b && odd_t) || yuv_16b;
// determine we's
web01_low <= !(load_dv && ((!a_twelve && !rgba_32b && !yuv_16b) ||
((rgba_32b || yuv_16b) && !(a_three ^ odd_t))));
web23_low <= !(load_dv && ((!a_twelve && !rgba_32b && !yuv_16b) ||
((rgba_32b || yuv_16b) && (a_three ^ odd_t))));
web01_high <= !(load_dv && ((a_twelve && !rgba_32b && !yuv_16b) ||
((rgba_32b || yuv_16b) && !(a_three ^ odd_t))));
web23_high <= !(load_dv && ((a_twelve && !rgba_32b && !yuv_16b) ||
((rgba_32b || yuv_16b) && (a_three ^ odd_t))));
end // always
assign di_high[63:0] = four_to_one(sel[1:0], copy_load_1d[63:0],
{copy_load_1d[31:0], copy_load_1d[63:32]},
{copy_load_1d[47:32], copy_load_1d[15:0],
copy_load_1d[47:32], copy_load_1d[15:0]},
{copy_load_1d[55:48], copy_load_1d[39:32],
copy_load_1d[23:16], copy_load_1d[7:0],
copy_load_1d[55:48], copy_load_1d[39:32],
copy_load_1d[23:16], copy_load_1d[7:0]});
assign di_low[63:0] = four_to_one(sel[1:0], copy_load_1d[63:0],
{copy_load_1d[31:0], copy_load_1d[63:32]},
{copy_load_1d[63:48], copy_load_1d[31:16],
copy_load_1d[63:48], copy_load_1d[31:16]},
{copy_load_1d[63:56], copy_load_1d[47:40],
copy_load_1d[31:24], copy_load_1d[15:8],
copy_load_1d[63:56], copy_load_1d[47:40],
copy_load_1d[31:24], copy_load_1d[15:8]});
endmodule // tm_load