/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vu.v,v 1.1 2002/03/28 00:26:14 berndt Exp $


/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vu						*
*	Description:	Top level vector unit which incorporates 4	* 
*			vector unit slice and one divide unit.		*
*			Each vector unit slice includes two vector 	*
*			unit datapaths, the unique control for each	*
*									*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		4/6/95						*
*									*
*************************************************************************
*/

// vu.v: 	RSP vector unit top level - instantiation of datapath and control

`timescale 1ns / 10ps

module	vu (	clk, reset_l, 
		su_instvld_rd, su_instvldk_rd, 
		su_storeinst_rd,
		su_vseqone_rd, su_instelem_rd, su_instfunc_rd, 
		su_rdcmpcd_rd, su_rdcryout_rd, su_rdcmpcdad_rd,
		su_wrcmpcd_wb, su_wrcryout_wb, su_wrcmpcdad_wb,

		su_st_rnum_rd,
		su_xp_rnum_rd,
		su_ld_rnum_ac,
		su_vs_addr_rd,
		su_vt_addr_rd,
		su_vd_addr_ac,
		su_wbv_wr_en_ac,
		su_bwe_ac,
		su_st_xposeop_rd,
		su_ld_xposeop_wb,

		su_data_to_from
	   ) ;


	input	clk;				/* vu clock */
	input	reset_l;			/* vu active low reset */

	input	su_instvld_rd;			/* valid CP2 instruction for vu without kill */
	input	su_instvldk_rd;			/* valid CP2 instruction for vu with kill */
	input	su_storeinst_rd;		/* store from VU */
	input	su_vseqone_rd;			/* vs field of instruction equal to 1 */
	input   [3:0] su_instelem_rd;		/* element field of instruction */
	input   [5:0] su_instfunc_rd;		/* function field of instruction */

	input	su_rdcmpcd_rd;			/* read vector compare code register */
	input	su_rdcryout_rd;			/* read vector carry out register */
	input	su_rdcmpcdad_rd;		/* read vector compare add register */

	input	su_wrcmpcd_wb;			/* write vector compare code register */
	input	su_wrcryout_wb;			/* write vector carry out register */
	input	su_wrcmpcdad_wb;		/* write vector compare add register */

/*
*	The following input signals are for register file address decoding
*	only.
*/

	input	[4:0]	su_st_rnum_rd;		/* register number for stores */
	input	[4:0]	su_xp_rnum_rd;		/* register number for xpose stores */
	input	[4:0]	su_ld_rnum_ac;		/* register number for load */
	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[4:0]	su_vt_addr_rd;		/* decoded register number for vt read */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */
	input		su_wbv_wr_en_ac;	/* write enable for datapath results */
	input	[15:0]	su_bwe_ac;		/* load port byte write enable */
	input		su_st_xposeop_rd;	/* store transpose op in rd */
	input		su_ld_xposeop_wb;	/* load transpose op in wb */

	inout	[127:0]	su_data_to_from;	/* data field to/from vu */
	
/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold and instruction decoding.
*
*/


/*
*	The following are wires for connecting between vector unit datapath slice
*	modules.
*/

	wire	vct_instvld01_ac;		/* valid CP2 instruction in AC */
	wire	vct_instvld23_ac;		/* valid CP2 instruction in AC */
	wire	vct_instvld45_ac;		/* valid CP2 instruction in AC */
	wire	vct_instvld67_ac;		/* valid CP2 instruction in AC */

	wire	vct_dvtypop01_ac;		/* divide op in ac stage from VU slice 01 */
	wire	vct_dvtypop23_ac;		/* divide op in ac stage from VU slice 23 */
	wire	vct_dvtypop45_ac;		/* divide op in ac stage from VU slice 45 */
	wire	vct_dvtypop67_ac;		/* divide op in ac stage from VU slice 67 */

	wire	[2:0]	vct_vs_addr01_ac;	/* vs address in ac stage from VU slice 01 */
	wire	[2:0]	vct_vs_addr23_ac;	/* vs address in ac stage from VU slice 23 */
	wire	[2:0]	vct_vs_addr45_ac;	/* vs address in ac stage from VU slice 45 */
	wire	[2:0]	vct_vs_addr67_ac;	/* vs address in ac stage from VU slice 67 */

	wire	[127:0]	vrf_vs_data_mu;		// vs port read data from register file
	wire	[127:0]	vrf_vt_data_mu;		// vt port read data from register file
	wire	[127:0]	vdp_rslt_data_wb;	// vd port write data from register file

	wire	[15:0]	vrf_div_input_rd;	/* data for divide unit */
	wire	[15:0]	vdi_divrslt_wb;		/* result from divide unit */

	wire	[3:0]	su_sclrdatasl_rd;	/* selcts for vector, quarter, half or whole scalar data */
	wire	[1:0]	su_qrtdatasl_rd;	/* selects for scalar quarter data */
	wire	[3:0]	su_hlfdatasl_rd;	/* selects for scalar half data */
	wire	[7:0]	su_whldatasl_rd;	/* selects for scalar whole data */

	wire	[4:0]	su_vd_addr_wb;		/* register number for datapath writeback */
	wire	[4:0]	su_ld_rnum_wb;		/* register number for load */

	wire	[7:0]	vct_wbv_wr_en_wb;	/* short word write enable for datapath results */
	wire	[15:0]	su_bwe_wb;		/* load port byte write enable */


vusl	vusl01 (
		.clk				(clk),
		.reset_l			(reset_l), 

		.vrf_vsdata0_mu			(vrf_vs_data_mu[127:112]),
		.vrf_vtdata0_mu			(vrf_vt_data_mu[127:112]),
		.vrf_vsdata1_mu			(vrf_vs_data_mu[111:96]),
		.vrf_vtdata1_mu			(vrf_vt_data_mu[111:96]),

		.su_instvld_rd			(su_instvld_rd),
		.su_instvldk_rd			(su_instvldk_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_rslt_data0_wb		(vdp_rslt_data_wb[127:112]),
		.vdp_rslt_data1_wb		(vdp_rslt_data_wb[111:96]),

		.vct_instvld_ac			(vct_instvld01_ac),
		.vct_dvtypop_ac			(vct_dvtypop01_ac),
		.vct_vs_addr_ac			(vct_vs_addr01_ac),

		.su_cont_to_from		({su_data_to_from[105:104],su_data_to_from[97:96]})

	   ) ;



vusl	vusl23 (
		.clk				(clk),
		.reset_l			(reset_l), 

		.vrf_vsdata0_mu			(vrf_vs_data_mu[95:80]),
		.vrf_vtdata0_mu			(vrf_vt_data_mu[95:80]),
		.vrf_vsdata1_mu			(vrf_vs_data_mu[79:64]),
		.vrf_vtdata1_mu			(vrf_vt_data_mu[79:64]),

		.su_instvld_rd			(su_instvld_rd),
		.su_instvldk_rd			(su_instvldk_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_rslt_data0_wb		(vdp_rslt_data_wb[95:80]),
		.vdp_rslt_data1_wb		(vdp_rslt_data_wb[79:64]),

		.vct_instvld_ac			(vct_instvld23_ac),
		.vct_dvtypop_ac			(vct_dvtypop23_ac),
		.vct_vs_addr_ac			(vct_vs_addr23_ac),

		.su_cont_to_from		({su_data_to_from[107:106],su_data_to_from[99:98]})

	   ) ;


vusl	vusl45 (
		.clk				(clk),
		.reset_l			(reset_l), 

		.vrf_vsdata0_mu			(vrf_vs_data_mu[63:48]),
		.vrf_vtdata0_mu			(vrf_vt_data_mu[63:48]),
		.vrf_vsdata1_mu			(vrf_vs_data_mu[47:32]),
		.vrf_vtdata1_mu			(vrf_vt_data_mu[47:32]),

		.su_instvld_rd			(su_instvld_rd),
		.su_instvldk_rd			(su_instvldk_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_rslt_data0_wb		(vdp_rslt_data_wb[63:48]),
		.vdp_rslt_data1_wb		(vdp_rslt_data_wb[47:32]),

		.vct_instvld_ac			(vct_instvld45_ac),
		.vct_dvtypop_ac			(vct_dvtypop45_ac),
		.vct_vs_addr_ac			(vct_vs_addr45_ac),

		.su_cont_to_from		({su_data_to_from[109:108],su_data_to_from[101:100]})

	   ) ;


vusl	vusl67 (
		.clk				(clk),
		.reset_l			(reset_l), 

		.vrf_vsdata0_mu			(vrf_vs_data_mu[31:16]),
		.vrf_vtdata0_mu			(vrf_vt_data_mu[31:16]),
		.vrf_vsdata1_mu			(vrf_vs_data_mu[15:0]),
		.vrf_vtdata1_mu			(vrf_vt_data_mu[15:0]),

		.su_instvld_rd			(su_instvld_rd),
		.su_instvldk_rd			(su_instvldk_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_rslt_data0_wb		(vdp_rslt_data_wb[31:16]),
		.vdp_rslt_data1_wb		(vdp_rslt_data_wb[15:0]),

		.vct_instvld_ac			(vct_instvld67_ac),
		.vct_dvtypop_ac			(vct_dvtypop67_ac),
		.vct_vs_addr_ac			(vct_vs_addr67_ac),

		.su_cont_to_from		({su_data_to_from[111:110],su_data_to_from[103:102]})

	   ) ;


vurfctl	vurfctl1	(	
			.clk				(clk),
			.reset_l			(reset_l), 
			.su_instelem_rd			(su_instelem_rd),
			.su_bwe_ac			(su_bwe_ac),
			.su_vd_addr_ac			(su_vd_addr_ac),
			.su_ld_rnum_ac			(su_ld_rnum_ac),
			.su_xposeop_rdac		(su_st_xposeop_rd),
			.vct_instvld_ac			(vct_instvld67_ac),
			.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
			.vct_dvtypop_ac			(vct_dvtypop67_ac),
			.vct_vs_addr_ac			(vct_vs_addr67_ac),

			.su_sclrdatasl_rd		(su_sclrdatasl_rd),
			.su_qrtdatasl_rd		(su_qrtdatasl_rd),
			.su_hlfdatasl_rd		(su_hlfdatasl_rd),
			.su_whldatasl_rd		(su_whldatasl_rd),

			.su_vd_addr_wb			(su_vd_addr_wb),
			.su_ld_rnum_wb			(su_ld_rnum_wb),

			.vct_wbv_wr_en_wb		(vct_wbv_wr_en_wb),
			.su_bwe_wb			(su_bwe_wb)

		) ;


vurf	vdpregfile_i (	
			.preclk_in0			(clk),
			.preclk_in1			(clk),
			.reset_l			(reset_l), 
			.su_instvld_rd			(su_instvld_rd),

			.su_vs_addr_rd			(su_vs_addr_rd),
			.su_vt_addr_rd			(su_vt_addr_rd),
			.su_vd_addr_wb			(su_vd_addr_wb),
			.su_st_rnum_rd			(su_st_rnum_rd),
			.su_xp_rnum_rd			(su_xp_rnum_rd),
			.su_ld_rnum_wb			(su_ld_rnum_wb),

			.su_sclrdatasl_rd		(su_sclrdatasl_rd),
			.su_qrtdatasl_rd		(su_qrtdatasl_rd),
			.su_hlfdatasl_rd		(su_hlfdatasl_rd),
			.su_whldatasl_rd		(su_whldatasl_rd),

			.vct_wbv_wr_en_wb		(vct_wbv_wr_en_wb),
			.su_bwe_wb			(su_bwe_wb),
			.su_xposeop_rd			(su_st_xposeop_rd),
			.su_xposeop_wb			(su_ld_xposeop_wb),

			.vdp_datatristen_rd		(su_storeinst_rd),
			.vdp_rslt_data_wb		(vdp_rslt_data_wb),

			.vrf_div_input_rd		(vrf_div_input_rd),
			.vrf_vs_data_mu			(vrf_vs_data_mu),
			.vrf_vt_data_mu			(vrf_vt_data_mu),
			.su_data_to_from		(su_data_to_from)

		) ;




div	div1  (
		.CLK				(clk),
		.Reset_l			(reset_l),
		.OpCode				(su_instfunc_rd),
		.OpCodeValid			(su_instvldk_rd),
		.VT				(vrf_div_input_rd),
		.DivOut				(vdi_divrslt_wb)
	      ) ;


endmodule