compile.scr
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/* compile.scr v1 Frank Berndt
* run the compile from prepared database;
*/
/*
* read the uniquified database;
*/
read db/uniq.db
/*
* include common scripts from NEC;
*/
include ../common/MUX_SCAN.scr
include ../common/set_wire_load.scr
/*
* compile the design;
* write out database and temporary gate level;
*/
compile
write -h -o ./db/bb.db
write -f verilog -h -o ./gate/gate.v
/*
* write out reports after compilation;
*/
report -area > ./report/bb.area
report -cell > ./report/bb.cell
report -hier -full > ./report/bb.hier
report_constraint -all_violators > ./report/bb.violations
report_timing -input_pins -nworst 5 -max_path 1000 > ./report/bb.timing
include ./script/report.scr > ./report/bb.report
check_design > ./report/bb.check
/*
* change gate level names;
* write out final gate level;
*/
include ../common/NAME_RULE.scr
change_names -rule OpenCAD -h
write -f verilog -h -o ./gate/bb.v
quit