/* fixes.scr v1 Frank Berndt
 * fixes to work around cell library problems;
 */

/*
 * virage cell libraries have problem from
 *	RECALL -> RCREAD
 *	COMP   -> RCREADY
 *	COMP   -> MATCH
 */
set_disable_timing nvrm_nc15gfh_64x32_MAX/nvrm_nc15gfh_64x32 -from RECALL -to RCREADY
set_disable_timing nvrm_nc15gfh_64x32_MAX/nvrm_nc15gfh_64x32 -from COMP   -to RCREADY
set_disable_timing nvrm_nc15gfh_64x32_MAX/nvrm_nc15gfh_64x32 -from COMP   -to MATCH
set_disable_timing nvrm_nc15gfh_16x32_MAX/nvrm_nc15gfh_16x32 -from RECALL -to RCREADY
set_disable_timing nvrm_nc15gfh_16x32_MAX/nvrm_nc15gfh_16x32 -from COMP   -to RCREADY
set_disable_timing nvrm_nc15gfh_16x32_MAX/nvrm_nc15gfh_16x32 -from COMP   -to MATCH

/*
 * disable virage SCLK->SO path;
 * virage has a path delay of 142ns on it;
 * but we don't want the rest of the JTAGCLK domain limited to 6MHz;
 * have to keep in mind when using the virage serial interface;
 */
set_disable_timing nvrm_nc15gfh_64x32_MAX/nvrm_nc15gfh_64x32 -from SCLK -to SO
set_disable_timing nvrm_nc15gfh_16x32_MAX/nvrm_nc15gfh_16x32 -from SCLK -to SO