/* io.scr v1 Frank Berndt
 * io constraints;
 * io related false paths are in this file;
 */

/*
 * dont_touch all pad IOs;
 * dont_touch all instantiated io buffers;
 */
set_dont_touch find(net, "PAD_*")
set_dont_touch find(cell, "pad_*")

/*
 * dont_touch instantiated oscillators;
 */
set_dont_touch usbclk_osc;
set_dont_touch vclk_osc;

/*
 * dont_touch pll analog nets;
 */
set_dont_touch { pllx2_avdd1 pllx2_agnd1 }
set_dont_touch { pllc_avdd1 pllc_agnd1 }
set_dont_touch { pllv_avdd1 pllv_agnd1 pllv_dvdd1 pllv_dgnd1 }

/*
 * dont_touch virage VPP probe pads;
 * dont_touch virage power nets;
 */
set_dont_touch find(net, "v_vpp*")
set_dont_touch { v0/vsc/n_PU1 v1/vsc/n_PU1 v2/vsc/n_PU1 }
set_dont_touch { v0/vsc/n_PU2 v1/vsc/n_PU2 v2/vsc/n_PU2 }

/*
 * PAD_RST_L into all clock domains;
 * used as both synchronous and asynchronous reset;
 */
set_input_delay 0.5 -clock SYSCLK -min { PAD_RST_L }
set_input_delay 1   -clock SYSCLK -max { PAD_RST_L }

/*
 * delays of misc input-only ports;
 * asynchronous input, sampled with SYSCLK;
 */
set_input_delay 0.5 -clock SYSCLK -min { PAD_BUTTON }
set_input_delay 1   -clock SYSCLK -max { PAD_BUTTON }

/*
 * digital video port;
 * synchronous output;
 * set output delay to 50% of cycle time to force flops close to pads;
 */
set_max_delay 2.0 -from VCLOCK -to PAD_VCLOCK
set_output_delay 0.5 -clock VCLOCK -min find(port, "PAD_VDATA*")
set_output_delay 0.5 -clock VCLOCK -min find(port, "PAD_VSYNC")
set_output_delay 10  -clock VCLOCK -max find(port, "PAD_VDATA*")
set_output_delay 10  -clock VCLOCK -max find(port, "PAD_VSYNC")

/*
 * analog video port;
 * PAD_VOA, PAD_VOB, PAD_VOC do not need constraints;
 * the wires from DAC to pads are dont_touch above;
 */

/*
 * audio port;
 * output synchronous to video clock;
 * set output delay to 50% of cycle time to force flops close to pads;
 */
set_output_delay 0.5 -clock VCLOCK -min { PAD_ACLOCK PAD_ADATA PAD_AWORD }
set_output_delay 10  -clock VCLOCK -max { PAD_ACLOCK PAD_ADATA PAD_AWORD }

/*
 * joy-channel ports;
 * bi-directional, asynchronous, sampled/driven by SYSCLK;
 * set output delay to 50% of cycle time to force flops close to pads;
 */
set_input_delay  0.5 -clock SYSCLK -min find(port, "PAD_JCHAN*")
set_input_delay  1   -clock SYSCLK -max find(port, "PAD_JCHAN*")
set_output_delay 0.5 -clock SYSCLK -min find(port, "PAD_JCHAN*")
set_output_delay 5   -clock SYSCLK -max find(port, "PAD_JCHAN*")

/*
 * local controller x/y sticks ports;
 * input only, asynchronous, sampled by SYSCLK;
 */
set_input_delay 0.5 -clock SYSCLK -min { PAD_LX0 PAD_LX1 PAD_LY0 PAD_LY1 }
set_input_delay 1   -clock SYSCLK -max { PAD_LX0 PAD_LX1 PAD_LY0 PAD_LY1 }

/*
 * io bus;
 * inputs sampled by SYSCLK, outputs driven from SYSCLK;
 * set io delays to 50% of cycle time to force flops close to pads;
 */
set_input_delay 0.5 -clock SYSCLK -min find(port, "PAD_IO_AD*")
set_input_delay 0.5 -clock SYSCLK -min { PAD_IO_DMARQ PAD_IO_INTR }
set_input_delay 5   -clock SYSCLK -max find(port, "PAD_IO_AD*")
set_input_delay 5   -clock SYSCLK -max { PAD_IO_DMARQ PAD_IO_INTR }

set_output_delay 0.5 -clock SYSCLK -min { PAD_IO_RST PAD_IO_ALE }
set_output_delay 0.5 -clock SYSCLK -min { PAD_IO_IOR PAD_IO_IOW }
set_output_delay 0.5 -clock SYSCLK -min find(port, "PAD_IO_AD*")
set_output_delay 0.5 -clock SYSCLK -min find(port, "PAD_IO_CS*")
set_output_delay 5   -clock SYSCLK -max { PAD_IO_RST PAD_IO_ALE }
set_output_delay 5   -clock SYSCLK -max { PAD_IO_IOR PAD_IO_IOW }
set_output_delay 5   -clock SYSCLK -max find(port, "PAD_IO_AD*")
set_output_delay 5   -clock SYSCLK -max find(port, "PAD_IO_CS*")

/*
 * flash bus, data move on PAD_IO_AD;
 * set io delays to 50% of cycle time to force flops close to pads;
 */
set_input_delay  0.5 -clock SYSCLK -min { PAD_FL_RYBY PAD_FL_MD }
set_input_delay  1   -clock SYSCLK -max { PAD_FL_RYBY PAD_FL_MD }
set_output_delay 0.5 -clock SYSCLK -min find(port, "PAD_FL_CE*")
set_output_delay 0.5 -clock SYSCLK -min { PAD_FL_ALE PAD_FL_CLE }
set_output_delay 0.5 -clock SYSCLK -min { PAD_FL_RE PAD_FL_WE PAD_FL_WP }
set_output_delay 5   -clock SYSCLK -max find(port, "PAD_FL_CE*")
set_output_delay 5   -clock SYSCLK -max { PAD_FL_ALE PAD_FL_CLE}
set_output_delay 5   -clock SYSCLK -max { PAD_FL_RE PAD_FL_WE PAD_FL_WP }

/*
 * gpio bus;
 * bidirectional, sampled and driven by SYSCLK;
 */
set_input_delay  0.5 -clock SYSCLK -min find(port, "PAD_GPIO*")
set_input_delay  1   -clock SYSCLK -max find(port, "PAD_GPIO*")
set_output_delay 0.5 -clock SYSCLK -min find(port, "PAD_GPIO*")
set_output_delay 5   -clock SYSCLK -max find(port, "PAD_GPIO*")

/*
 * usb;
 * dont_touch transceiver cells;
 * output jitter is spec'ed at -2..5, constrain to 5ns;
 */
set_dont_touch { usb_xcvr0/plus_buf usb_xcvr0/minus_buf usb_xcvr0/bias }
set_dont_touch { usb_xcvr1/plus_buf usb_xcvr1/minus_buf usb_xcvr1/bias }
set_output_delay 1.0 -clock USBCLK -min { PAD_USB_DPLUS0 PAD_USB_DMINUS0 }
set_output_delay 1.0 -clock USBCLK -min { PAD_USB_DPLUS1 PAD_USB_DMINUS1 }
set_output_delay 6.0 -clock USBCLK -max { PAD_USB_DPLUS0 PAD_USB_DMINUS0 }
set_output_delay 6.0 -clock USBCLK -max { PAD_USB_DPLUS1 PAD_USB_DMINUS1 }
set_input_delay  6.0 -clock USBCLK -max { PAD_USB_DPLUS0 PAD_USB_DMINUS0 }
set_input_delay  6.0 -clock USBCLK -max { PAD_USB_DPLUS1 PAD_USB_DMINUS1 }

/*
 * usb pull drivers;
 */
set_output_delay 3 -clock SYSCLK -max { PAD_USB_DP_HIGH0 PAD_USB_D_LOW_N0 PAD_USB_VBUS_ON_N0 }
set_output_delay 3 -clock SYSCLK -max { PAD_USB_DP_HIGH1 PAD_USB_D_LOW_N1 PAD_USB_VBUS_ON_N1 }

set_input_delay  1 -clock SYSCLK -max { PAD_USB_VBUS_VLD0 PAD_USB_ID0 }
set_input_delay  1 -clock SYSCLK -max { PAD_USB_VBUS_VLD1 PAD_USB_ID1 }

/*
 * test and others;
 */
set_dont_touch { tmc tmc1 tmc2 nectrst }

/*
 * false paths in the test environment;
 */
set_false_path -from PAD_NRING_ENL
set_false_path -from PAD_JTAG_EN
set_false_path -from vtestena/ena